Benedikt wrote on Yesterday, 17:25:

PSA: The PCB layout on page two of ISA-CGA6845-1.5.pdf is a largely complete vector drawing of all layers, i.e. you can open it […]
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PSA: The PCB layout on page two of ISA-CGA6845-1.5.pdf is a largely complete vector drawing of all layers, i.e. you can open it in Inkscape and take it apart.

Furthermore, it occurred to me that, since the card has 32 KiB of SRAM, it should be possible to modify it for Plantronics ColorPlus style 16-color graphics.
The hardware part of the modification would only require one bodge wire to the SRAM's highest address line.
We would then also need new bitstreams for the CPLDs, but that should be doable, too.
The memory bandwidth for 320x200x16 and 640x200x4 should be the same as in 80-column text mode.
It should also be possible to fix the wait state generation to get rid of the CGA snow that would otherwise also affect the new modes.

Card and spare CPLDs are on their way. Let's see where this takes us...

Uh, that's fascinating. So you would write the CPLD code from scratch?

root42 wrote on Today, 05:23:

Uh, that's fascinating. So you would write the CPLD code from scratch?

The idea is to use a slightly byzantine tool chain consisting of GHDL, a Yosys fork for the ATF15xx CPLDs, and the old Atmel fitters.
That way, everything can be modeled in VHDL instead of CUPL and the resulting library of assorted 74xx logic chip VHDL models can be reused for all sorts of things.