I am acutally quite surprised that the AHA-2842 helps with the floppy issue. It has a standard Intel 82077 floppy controller (which supports 2.88MB floppy drives and floppy streamers at 1MBit/s), but that one is connected to the ISA bus like any other floppy controller is as well, and it uses ISA DMA channel 2 like any other floppy controller. I also don't think the I saw some cache workarounds in the BIOS of the 2842, when looking at EDD support for it (although I don't specifically remember looking at the 2842A, just at the 2842VL, the earlier revision of that card).
On the other hand, I do understand that the bus-mastering VL SCSI controller has WB support (which may be disabled using a jumper). On compatible mainboards with that jumper set, the SCSI part is supposed to work perfectly with L1WB. Removing that jumper will break L1WB operation, but may fix L1WT operation on incompatible mainboards.
Indeed, the key point to get L1WB working is to have
- The HITM pin from the processor routed to the correct pin of the chipset
- The chipset in the correct mode to wait for and recognize the HITM signal on every ISA DMA cycle
- The processor receive a valid INV signal on DMA writes
The first item requires correct processor type jumpering. Jumpering for a Enhanced DX2 WB processor or an Enhanced DX4 WB processor should include the correct routing of the signals. HITM* from the processor socket is supposed to be connected to pin 90 of the SiS 471.
The second item typically requires proper initialization of the chipset by the BIOS, but in the case of the 471, the hardware "traps" (nowadays, we call stuff like this "straps") need to be set appropriately as well. Bit 4 of chipset register 50 needs to be set if a L1WB processor is operating in L1WB mode. As the datasheet says, the BIOS should only set that bit if the traps are set to either Cyrix M6/M7 or P24D/T mode. The AMD 5x86 is compatible with the P24D/T mode, and incompatible with the Cyrix M6/M7 mode, so you require the traps to be set to P24D/T and the cache mode bit needs to be set. JP5 and JP6 need to bne set in a way that pins 190 and 191 are both pulled high (possibly that is what the setting "both to 1-2" does). For setting the cache mode bit, you rely on the BIOS to do the correct thing, and that may be a problem: You recognize WB processors by them having specific "well-known" CPU IDs. The AMD 5x86 in 4x clock mode uses CPU IDs no other processor used before, so if a BIOS is older than the 5x86 (aka X5 or DX5) specification, the ID is not "well-known", and the chipset will not be prepared for L1WB operation. Intel and AMD CPUs can not be software-configured to L1WB or L1WT, but they rely entirely on hardware strapping, so a working L1WB solution for Intel/AMD requires the WB/WT jumper to enable the L1WB enhanced bus protocol, the chipset (s)trapping and the L1WB enable bit of the chipset all to be in sync, or bad things will happen, so with a BIOS that doesnt support the 5x86, you are out of luck, at least in 4x mode. In 3x mode, the CPU ID of an AMD 5x86 looks similar enough to WB-enabled Intel DX4 processors, so a BIOS supporting those Intel processors might support the 5x86 in "DX4 mode" as well.
The this item is usually acomplished by shorting the INV pin with the W/R pin at the 486 socket, which is done using a jumper.
The L1WB mode in the BIOS setup will enable or disable the software-controlled L1WB mode of Cyrix processors, and if the BIOS is behaves remotely sensible, also configure the chipset accordingly if a Cyrix processor is installed, but the effect of that BIOS option for Intel and AMD processors is not well-defined. As the L1WB mode of those processors is hardware defined, it does not really make sense to configure the chipset based on a software option instead of the CPU ID. On the other hand, it makes some sense to let the expert user override the CPU-ID based determination of the WB/WT mode of Intel/AMD processors in case the CPU ID is not clearly recognized. So there are reasons to ignore this option for Intel/AMD and reasons to apply this option for Intel/AMD.
You can verify the connection of HITM* to the chipset and of INV to W/R using a continuity checker. You can also verify whether the traps are both pulled up using electrical measurements (likely JP5/6 have pin 1 to Vcc/GND, pin 3 to GND/Vcc and pin 2 via 2k2 to the corresponfing trap pin). You can only hope the BIOS does the right thing if the hardware settings all line up perfectly.
