Was it already proven that pin 24 of the feature connector goes to the PEGA2 directly? If so I missed it. And I was thinking maybe the PAL is additional layer of logic, for whatever purpose, over something else and it's that something else before it that died.

One another idea I have is to check where the pin 11 of the PAL goes to. It can be configured as input or /OE signal for pins 12-19. GALs have more options but this is just a PAL, should be more dumb. So perhaps the outputs are tri-stated for some reason? And that makes the HSYNC simply float.

mkarcher wrote on 2025-07-21, 16:31:

That's possibly good news, as this makes it more unlikely that the PAL is the cause of the issue, but the missing HSYNC is likely already missing before the PAL. Could you find a PAL pin connect to pin 24 of the feature connector? It looks like there is a fault on the HSYNC signal before the PAL, and pin 24 of the feature connector is supposed to be "hsync as generated by the card".

Pin 24 of the feature connector goes under DIP Switch 🙁

mkarcher wrote on 2025-07-21, 17:34:

butjer1010 wrote on 2025-07-21, 17:27:

I was flux residue, not broken trace 😀 Didn't saw it at all

OK, I have another idea. Assuming the PAL is broken and shorts pin 13 to ground. This would kill the HSYNC signal even if you bypass the PAL. With the wire between pins 30 and 24 still installed at the feature connector, remove U20 from the socket, bend pin 13 upwards, so it does not get into the socket, and re-insert the PAL without pin 13 connected. This should ensure the PAL is unable to interfere with the sync signal from the PEGA2A chip.

I will do that and let You know

Deunan wrote on 2025-07-21, 17:49:

Was it already proven that pin 24 of the feature connector goes to the PEGA2 directly? If so I missed it. And I was thinking maybe the PAL is additional layer of logic, for whatever purpose, over something else and it's that something else before it that died.

One another idea I have is to check where the pin 11 of the PAL goes to. It can be configured as input or /OE signal for pins 12-19. GALs have more options but this is just a PAL, should be more dumb. So perhaps the outputs are tri-stated for some reason? And that makes the HSYNC simply float.

We did write posts at the same time 😀
Yes, pin 24 goes under dip switch, so probably direct to the PEGA2 chip

Deunan wrote on 2025-07-21, 17:49:

Was it already proven that pin 24 of the feature connector goes to the PEGA2 directly?

Not proven, but it is very likely. I followed the traces on the pictures posted in this thread. As butjer1010 correctly identified, pin 24 of the feature connector disappears below the DIP switch. There are no vias below the dip switches, and ther are 10 lines disppearing on the "slot bracket" side and 10 line reappearing on the "PEGA2A" side. The trace connected to pin 24 of the feature connector is the top trace of those 10 traces, which ends in a via directly next to the DIP switch and is connected to the PEGA chip on the solder side.

mkarcher wrote on 2025-07-21, 18:13:

Deunan wrote on 2025-07-21, 17:49:

Was it already proven that pin 24 of the feature connector goes to the PEGA2 directly?

Not proven, but it is very likely. I followed the traces on the pictures posted in this thread. As butjer1010 correctly identified, pin 24 of the feature connector disappears below the DIP switch. There are no vias below the dip switches, and ther are 10 lines disppearing on the "slot bracket" side and 10 line reappearing on the "PEGA2A" side. The trace connected to pin 24 of the feature connector is the top trace of those 10 traces, which ends in a via directly next to the DIP switch and is connected to the PEGA chip on the solder side.

It is connected with this pin on PEGA (picture)

butjer1010 wrote on 2025-07-21, 18:05:

mkarcher wrote on 2025-07-21, 17:34:

butjer1010 wrote on 2025-07-21, 17:27:

I was flux residue, not broken trace 😀 Didn't saw it at all

OK, I have another idea. Assuming the PAL is broken and shorts pin 13 to ground. This would kill the HSYNC signal even if you bypass the PAL. With the wire between pins 30 and 24 still installed at the feature connector, remove U20 from the socket, bend pin 13 upwards, so it does not get into the socket, and re-insert the PAL without pin 13 connected. This should ensure the PAL is unable to interfere with the sync signal from the PEGA2A chip.

I will do that and let You know

Yeeeeeees, it work!!!!!!!!!!!!!!!!!!!!!!!!!
Now i need to find DIP switch settings that are the best for EGA! Do You have any "favorite" combination? 😀 (this one is 0100)

0001

1110 (looks best to me so far)

1100 and 1001 looks same to me 😀

So, only 0001 and 1110 looks normal. Should i play some games to see which combination is better for this monitor?

So is output on the PAL dead or is it tri-stated? Perhaps it would still be worthwhile to trace pin 11 connection. I would not be using this card with direct output of PEGA2 on the connector for anything other than short testing, it might damage the chip.

EDIT: Probably dead if it didn't work with the wire bypass. Does the card still work if the PAL to the right (below the capacitors that smoked) is removed from socket? I wonder if these are swapped after all.

Deunan wrote on 2025-07-21, 18:47:

So is output on the PAL dead or is it tri-stated? Perhaps it would still be worthwhile to trace pin 11 connection. I would not be using this card with direct output of PEGA2 on the connector for anything other than short testing, it might damage the chip.

I was too fast 🙁 hope i didn't damage anything....
Prince with 1110, (1,2,3 on, 4 off, all other off)
I didn't try without this right PAL, should i?

I'm posting it again in case my edit above is missed: Probably PAL is dead if it didn't work with the wire bypass. Does the card still work if the PAL to the right (below the capacitors that smoked) is removed from socket? I wonder if these are swapped after all.

Deunan wrote on 2025-07-21, 18:51:

I'm posting it again in case my edit above is missed: Probably PAL is dead if it didn't work with the wire bypass. Does the card still work if the PAL to the right (below the capacitors that smoked) is removed from socket? I wonder if these are swapped after all.

Should i swap them, or try without right one?

Remove the right one first. If it breaks the card then it's a good chance that one is correct, thus no point in swapping them.

Deunan wrote on 2025-07-21, 19:03:

Remove the right one first. If it breaks the card then it's a good chance that one is correct, thus no point in swapping them.

Yes, it beeps when removed

Well then either that PAL output is broken or, perhaps, there is a problem with the input. If the PAL outputs HSYNC then it must also be getting it from the PEGA2 chip. See if you find a connection between pin 24 of the extension connector and one of the PAL pins. Maybe that is broken and the output is simply stuck at zero all the time.

butjer1010 wrote on 2025-07-21, 18:44:

So, only 0001 and 1110 looks normal. Should i play some games to see which combination is better for this monitor?

OK, let's look at your working combinations: All of your pictures show 200-line modes. This might be due to some CGA emulation mode being active in text mode (activated by the upper switches), or it might be that only 200-line modes work. If you limit yourself to the "officially allowed" configurations, you would expect to hit the 80x25 200-line text mode more often than the 40x25 mode. It seem the BIOS doesn't limit the switches to the allowed configurations, though, creating "ghost configurations" that may or may not work sensibly.

From your pictures, I deduce

• 40-character 200-line mode at 0100, 1100, 1001.
• 80-character 200-line mode at 0001 and 1110.

80-character mode at those two combinations makes perfect sense, as those combinations (read with inverted logic and most significant bit on the right) are "EGA primary card with CGA monitor in 80-character mode" (configuration 7), and "EGA primary card with EGA monitor, displaying text as a CGA card would, startup in 80-character mode" (configuration 8 ). If that logic is correct, we can deduce the switch setting that is supposed to yield "EGA primary card with CGA monitor in 40-character mode" (configuration 6), which is 1001, and that's actually also one of the working configuration, so I guess we decoded how the switch settings can be translated to configuration numbers. This allows me to read 0100 as "configuration 13" and 1100 as "configuration 12", which are both unsupported configurations. The BIOS has a 12-entry "switch interpretation table" which is assigned to configurations number 0 to 11. Configurations 12, 13, 14 and 15 accesses data as "switch interpretation" that is not meant to be used that way. Most prominently, configurations 12 and 13 will cause the BIOS to initialize the EGA card for a color monitor, while 14 and 15 will cause the BIOS to initialize the EGA card for a monochrome monitor. So it's not surprising that 12 and 13 cause your card to display an image, while 14 and 15 do not.

Something is still wrong, though. Assuming your monitor actually is an EGA monitor (and not just a CGA monitor), you should be able to get a considerably better text mode at 0110 (configuration 9). If that switch setting does not produce a stable image on an EGA monitor, something is wrong with the 16.257MHz oscillator, the oscillator selection circuit or the vertical sync polarity selection. The vertical sync polarity selection is completely integrated in the PEGA2A chip, so at the moment I consider it unlikely to be broken. Can you please post a photo of the screen contents at 0110, maybe during POST, or at the DOS prompt when AUTOEXEC is finished?

Deunan wrote on 2025-07-21, 19:14:

Well then either that PAL output is broken or, perhaps, there is a problem with the input. If the PAL outputs HSYNC then it must also be getting it from the PEGA2 chip. See if you find a connection between pin 24 of the extension connector and one of the PAL pins. Maybe that is broken and the output is simply stuck at zero all the time.

PALs PIN 11 and 13 are connected with PIN24(and 30 of course, wired) of feature connector