dionb wrote on 2024-11-06, 15:48:

[...]so probably here there is also an issue with the address lines to the chipset[...]

Hi, could you elaborate on that bit, @dionb?
This 'density' issue is very interesting to me because of how difficult to understand it seems, perhaps because it's complexity causes the information always missing something out.

Thank you.

AngryByDefault wrote on 2024-11-06, 18:14:

Hi, could you elaborate on that bit, @dionb? This 'density' issue is very interesting to me because of how difficult to understa […]
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dionb wrote on 2024-11-06, 15:48:

[...]so probably here there is also an issue with the address lines to the chipset[...]

Hi, could you elaborate on that bit, @dionb?
This 'density' issue is very interesting to me because of how difficult to understand it seems, perhaps because it's complexity causes the information always missing something out.

Thank you.

There's nothing complex about the density part so long as people stop vague "high" and "low" nonsense. A memory controller supports a certain density of memory chips. You can (or should be able to) look up what density is supported in the datasheet of the device.

The datasheet of the i430TX chipset is clear on the matter:
https://web.archive.org/web/20080224042728/ht … ts/29055901.pdf

The DRAM interface supports 4 Mbytes to 256 Mbytes with six RAS lines. The MTXC supports 4-Mbit, 16-Mbit,
and 64-Mbit DRAM and SDRAM technology,

So 64Mb chips are the highest officially supported. That means a 64MB DIMM with 8 chips of 64Mb each is explicitly supported.

But... your 64MB DIMM with 64Mb chips is being detected as a 16MB DIMM, as if it contained 16Mb chips. That means something is wrong. That means going a level deeper. To address the 64Mb chips requires 14 address lines, where 16Mb chips could be addressed with just 12. Now, reading the datasheet description of the memory interface I see this:

Note: For 64Mbit SDRAM support, BA1/MA12 and MA13 are muxed with the
RAS4# and RAS5# signals, respectively. When SDRAMC[bit 1]=1, BA1 and MA13
are driven out on these lines.

So the chipset only has 12 physical address lines and multiplexes MA12 and MA13 signals onto two of the RAS lines (RAS4 and 5), controlled by SDRAMC, the SDRAM controller.

Looking a bit further at the SDRAM controller I see this in the SDRAM control register:

64-Mbit Technology Enable (64MTEN). 1=Enable. 0=Disable. When set to 0, the MTXC does not support 64-Mbit SDRAM devices. In this […]
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64-Mbit Technology Enable (64MTEN). 1=Enable. 0=Disable. When set to 0, the MTXC does not
support 64-Mbit SDRAM devices. In this mode, the MTXC supports 4-Mbit, 16-Mbit, and 64-Mbit
technology for EDO/FPM systems and 4 Mbit and 16 Mbit for SDRAM systems (i.e., 64 Mbit not
supported in SDRAM systems). When set to 1, the MTXC supports 4 Mbit, 16 Mbit, and 64 Mbit
for both SDRAM and EDO/FPM devices. In this mode, the RAS#/CS5# signal becomes
RAS#/CS5#/MA13, RAS4#/CS4# becomes RAS4#/CS4#/BA1, and KRQAK/CS4_64# becomes
CS4_64#. CS4_64# (fifth row) function is provided if this signal is set to 1 and DRAM Cache is not
present in the system (indicated by a 0 in bit 5, register 53h)

So, we have a couple of ways in which this might go wrong:
- the board happily supports 64Mb in hardware, but the 64MTEN register isn't being set (by BIOS)
- the board lacks the ability to demux MA12 and MA13 into separate address lines to the RAM (never seen this, but possible)
- the board has all correct hardware and software, but the traces of MA12 and/or MA13 are damaged.

Now, the motherboard manual says:

Die Hauptplatine unterstützt in den DIMM-Sockeln Module der Größen 8 MB, 16 MB, 32 MB und 64
MB

So 64MB DIMMs are explicitly supported, and that implies 64Mb chip density support, as there's no way to get to 64MB using 16Mb chips within spec (x64 per bank)

That means that it's unlikely to be lack of hardware support for demux - although this is PC Chips and I wouldn't put it past them to cut corners there and brazenly ignore that in the manual...

Given that point, I dug a bit deeper into the "Intel 430TX PCIset Desktop Design Guide":
https://theretroweb.com/chipset/documentation … f0398505276.pdf

Here I see:

64-Mbit SDRAM Support—This feature is supported on A-1 MTXC. A-0 MTXC does not support
64-Mbit SDRAM.

This refers to the stepping of the FC82439TX northbridge. A-0 does not support 64Mb SDRAM, A-1 does. Problem: I've not found any way to identify which stepping your chip has...

If it's the old one, it's game over.

Edit: found it - https://www.cpu-world.com/sspec/SL/SL238.html

A-1 stepping has SL-code SL238. A-0 steppings were only used in engineering samples (Qxxx instead of SLxxx)

DIMM wiring guideline •• Connect MA11/BA0 to pin 122 of DIMM (BA0 for SDRAM, A11 for EDO/FPM) •• Connect RAS4#/CS4#/BA1 to pins […]
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DIMM wiring guideline
•• Connect MA11/BA0 to pin 122 of DIMM (BA0 for SDRAM, A11 for EDO/FPM)
•• Connect RAS4#/CS4#/BA1 to pins 39 and 126 of DIMM (BA1, A12 for SDRAM, A12 for
EDO/FPM)
•• Connect RAS5#/CS5#/MA13 to pin 123 of DIMM (A11 for SDRAM, A13 for EDO/FPM)

Those are specifically the traces you should be checking for damage. If those A12/A13 pins aren't being fed correctly that could explain a thing or two.

Apart from that - is there a newer BIOS version available? If it's a register not being set, that could fix.

@dionb

wow! That was some detailed feedback!

Thank you for taking all those troubles to help me understand this matters.

While so far I had a general grasp of it, most of what you just posted is way beyond what one would usually find about it (you know that, o.c.), so most of the "whys" and the technical implications are simply unknown to those of us not having some level of required knowledge.

I'll have to re-read your post a couple of times to and even lookup the precise implications of some terms within this context, but you've already broadened my understanding on this.
Thank you!

PS: just to avoid any confusion, I'm not the OP so I can't answer about the board's traces or BIOS.

Bottom line is just look up the actual chip density (number, not vague term) supported by the board and/or chipset, and calculate what density your DIMM has (capacity divided by number of chips, multiplied by 8 for bits vs Bytes). If the density of the DIMM (or SIMM for that matter) is lower or equal to what the chipset it supports, then you're good. If not, it will not be fully detected.

You only need to go as deep as I just did if the board isn't doing what you'd expect based on those specs.

dionb wrote on 2024-11-04, 10:59:

PoweredByJenga wrote on 2024-11-04, 10:14:

I know that this is an old post... but it may help pple in the future.
Vast majority of board up until about 1996/7 time could only take SDRAM which used 16Mb chips. Most 32MB DIMMs manufactured were double-sided — essentially a pair of 16MB DIMMs mounted back-to-back on a single circuit board — and each side had eight 16Mb chips to make 16MB, or 32MB in total.

Most 64MB DIMMs were single-sided, and used eight 64Mb chips. And this is where the problems start, for most older mainboards do not understand 64Mbit chips and see a standard 64MB DIMM as eight 16Mbit chips. Similarly, they see a typical double-sided 128MB DIMM as sixteen 16Mb chips and report only 32MB.

Totally true for i430VX and Via VPX - but this board has i430TX, which can definitely handle 64Mb chips in-spec (and 128Mb chips out-of-spec as well). So whatever is wrong, it's not a chipset limitation. Best guess is perhaps a damaged trace somewhere, but OP never did get to the bottom of it.

Hello,

I recently picked up a VIA VPX based board and remembering this thread, got intrigued about this again (long ago I ran into it on SiS 5571) and dug into it.

The VPX technically supports 64Mbit SDRAM but can also be used in VP-compatible pinout, in which case the pins repurposed on the VPX for 64Mbit support retain their prior function instead. This board uses VP-compatible pinout, so the necessary pins are not routed to where they should be on the DIMM socket, and the board can't handle 64Mbit.

I was exploring the fact that on other threads, sometimes you can use a DIMM that is 4x as big and it's seemingly working.

Looking at exactly what changes between 16Mbit and 64Mbit chips the difference is two pins. SDRAM chips are internally divided into banks (nothing to do with ranks or sides); 16Mbit has two banks and therefore one bank enable line; convention seems that MA11 from the chipset goes to BE0 when using 16Mbit. 64Mbit is four banks and therefore gains a second bank enable line, and gains an A11 pin.

So, the trick of using a 256MB DIMM made up of sixteen 16Mx8 (128Mbit) chips, as if it were a 64MB DIMM, rather than chasing down a elusive 32-chip 64MB DIMM is working. Each chip is 4M x 8 bits x 4 banks, but because this board can't control one column address line and one bank enable line, it sees the chips as 2M x 8 bits x 2 banks, and 4 megabytes per chip times 16 chips is 64MB as expected.

I have a twofold question about how reliable this actually is. One, this board is a little glitchy anyway (intermittent issues detecting secondary IDE), but with the 64MB DIMM, on hard power-ons sometimes it detects 64MB as expected, but other times random smaller amounts like 3 or 4MB. The reset switch (without a hard power off) does gets 64MB working again. Maybe this is just because the board had a lot of dust on QFP pins, so I'm cleaning them, or is it a worse issue: in this configuration, do A11 and BE1 on the oversized DIMM just float, or does the DIMM socket, DIMM, or SDRAM chip itself take care of having a pullup on those pins? Issues specifically tied to initial power-on noise might be tied to them floating?

Second, I can't find a thread now, but someone brought up whether the SDRAM would be refreshed correctly when the board isn't touching two of its addressing lines like this, or if it's irrelevant, since you aren't using the unrefreshed area in the SDRAM anyway.

edit: When it detects all 64MB, it's perfectly fast, and seems reliable enough including booting into NetBSD.

Cleaning the motherboard didn't fix the 3MB/4MB detection issue, but so far, pullups on BA1 and A11 of the DIMM has, but it's unfortunate if this isn't universal and some board+DIMM combinations might require adding resistors to the DIMM

Yeah, the symptoms you cited are typical for floating CMOS pins: When you power it up, the input may float somewhere in the middle between GND and Vdd (3.3V), and the digital level seen by the DRAM might fluctuate during RAM sizing. This is due to the mainly capacitive coupling of the gates at the CMOS inputs to Vcc and GND. If the capacities to Vcc and GND are roughly similar, you will get around 1.6V when the voltage at Vcc jumps from 0V to 3.3V. Due to leakage current (the coupling is not plainly capacitive, but a tiny resistive contribution is there as well), these pins will "slowly" float to a voltage that is either "clearly high" or "clearly low". That's why it works after reset, but not directly after power on.

Adding pull-ups is a correct way to handle this issue, probably pull-downs would work as well, the important point being that the level is not in the undefined region between high and low. I'd expect a 10K pullup on a 256M DIMM on the A11 and BA1 lines is a universal solution that should work on every board. You can even apply this to the DIMM, and it will work as 64M in old boards and as 256M in more recent boards.

mkarcher wrote on Yesterday, 10:19:

Adding pull-ups is a correct way to handle this issue, probably pull-downs would work as well, the important point being that the level is not in the undefined region between high and low. I'd expect a 10K pullup on a 256M DIMM on the A11 and BA1 lines is a universal solution that should work on every board. You can even apply this to the DIMM, and it will work as 64M in old boards and as 256M in more recent boards.

I had ended up with this, which seems to work fine.