Lotech makes a 1mb 8bit expansion card that does this very thing.

https://texelec.com/product/lo-tech-1mb-ram/

You would flip the switches to turn off the first 4 64k banks, since you have 256k on board.

Other than thatn you just plunk it in.

As for what's needed, yeah, just bus transiever buffers and driving the C/S line, more or less.

That is a very neat and versatile solution! Thanks for sharing that.

Looking at the Lo-tech 1MB RAM solution and given you last sentence, is it correct to say that a buffer for the data bus is really needed?

Taking that into account, I would come to the schematic as attached to this post. Anything I am overlooking?

Actually, I came across the explanation of the Lo-tech 1MB board here and also studied their schematic.

They note that the 74HCT245 is used to ensure proper compatibility with TTL logic levels, so I’ve followed the same approach in my design. The Lo-tech board is very versatile and allows mapping in 64 KB blocks, which is more flexibility than I need, so I’ve left that feature out. I also replaced my 3x128 KB SRAM chips for a single 512 KB SRAM chip, which is actually cheaper and I’ve chosen (compared to the Lo-tech design) for THT devices instead of SMD parts for easier prototyping and assembly. Attached to this post I show the revised schematic and a rendering of the PCB.

I am going to order a prototype and see if it works. Fingers crossed.

ifilot wrote on 2025-08-24, 06:12:

RAM must respond not only to CPU memory cycles but also DMA cycles. My plan here is **not** to use AEN — only to look at the address range and then gate the SRAMs with MEMR and MEMW signals from the ISA bus.

That's correct. Memory cards do not need to distinguish CPU and DMA cycles, both just look like memory reads and writes on the ISA bus. That's actually one of the key points of the ISA DMA design (which is suboptimal in a couple of other aspetcs, though). It's I/O cards that have to pay the price: As IBM decided to assert /IOW or /IOR on DMA cycles, and during a DMA cycle, a memory address is on the ISA bus, I/O address decoding needs to be qualified by AEN, and suppressed during DMA cycles. DMA targets respond to the simultaneous assertion of their DACK signal and /IOW or /IOR, so the DMA target knows the direction of the transfer. A design alternative could have been to have dedicated /DMAW and /DMAR signals that were asserted in combination with a per-channel DACK signal, or dedicated /DACKR and /DACKW signals per channel. Both variantes would increase the pin count, though.

In practice, this means any I/O target needs to decode AEN as is it were another I/O address bit and not respond if AEN is high.

ifilot wrote on 2025-08-24, 06:12:

Address decoding: Is expanding conventional RAM over the ISA bus really as simple as using glue logic so that /CS is asserted when the CPU addresses fall within the appropriate regions (i.e., 256–640 KiB)? Or are there pitfalls I should be aware of with the 5150’s memory map and bus timing?

As far as I know, the address lines are supposed to be valid the whole time while /MEMW or /MEMR is asserted, so it is actually that easy.

ifilot wrote on 2025-08-24, 06:12:

Bus buffering: Are buffer chips like the 74HCT245 (or even 74ACT245) required, or just best practice? The AS6C1008s have fairly low VIH thresholds, and I’ve used them reliably with LS-series logic in other retro systems — but I don’t know if the extra loading on the 5150’s ISA bus makes buffering more important here.

The key point you need to consider for the buffers is the output drive strength. If I remember correctly, the IBM bus is specified for 2 LS-TTL loads per slot plus some loads on the mainboard, and defined that a 74LS244/74LS245 is strong enought to drive the bus, which limits the number of ISA slots to 7. IBM placed the 8th slot in the XT on a separately buffered data path to avoid issues. If you can make sure that VOL is low enough even with around 20 LS-TTL loads pulling the data line high, you may get away without the buffer.

Thanks for the very clear explanation. Appreciated! 😀

I'll definitely leave the buffer in then.

ifilot wrote on 2025-08-24, 17:24:

Thanks for the very clear explanation. Appreciated! 😀

I'll definitely leave the buffer in then.

Depending on your video card and installed devices you may be able to locate more than 640k base memory and also can have UMBs

That’s why the lotech device allows you to turn on ram above 640k in case you have free banks to locate ram.