When the second TMU is enabled in hardware, the card works fine, but with only 1 TMU actually used.

I have tried many regular drivers, the Q3D Ventana 50 driver, different BIOS images, even the Q3D Ventana 50 BIOS, no difference.

On a Q3D Ventana 50, when installing an Amethyst module, it freezes when running a 3D application (http://www.thedodgegarage.com/3dfx/).

The card layout looks like this:

Unlike the OG Voodoo, which has dual TMU support even in the retail drivers, the existing Rush drivers have no support for it.

Unless the Rush driver source code somehow appears on the internet, this is it for this card. (Edit: https://github.com/sezero/glide , VG96 sources seem to be there, so it might be possible).

It was an interesting test though, and I found out some new things, some of which weren't available on the internet, and I will describe below.

The Voodoo Rush chipset is made from: 2D IC (AT25/AT3D or the Macronix one), FJR (which stands for FBI Junior) and the TMU (which is the same TMU used on the OG Voodoo).

The 2D ICs are made specifically for Rush cards, it is not possible to use another 2D IC, as there is a dedicated bus for talking to the FJR (probably for memory arbitration).

AT25/AT3D are interchangeable, they have the same pinout.

Some articles mention that the Rush has low performance because the 2D IC and FJR fight for PCI access. While they do fight for access in many ways, the FJR is actually not connected at all to the PCI bus, only the 2D IC is connected there. Everything goes through the 2D IC.
The 2D IC and FJR share a small bus, called the THP bus. This consists of the following signals (seen at the FJR side):

Besides that, the FJR and 2D IC are connected to the same RAM ICs. Literally the full memory controller of the 2D IC connected to the RAM ICs connected to the full memory controller of the FJR. ADDR, DATA, RAS, CAS, OE, WE.

The 2D IC generates the FJR and TMU clock. Besides this, there is no other connection between the 2D IC and the FJR. This diagram shows the major components and how they are connected:

On AT25/AT3D cards, the clock generated by the 2D IC goes through an AV9170-1 clock synchronizer before feeding the FJR/TMU. This IC is used on all AT Rush cards out there. While some cards have an option to bypass it on the PCB, bypassing it will result in a non-working Rush. Possible reasons: DC offset on AT output clock/clock needs a negative phase offset for things to sync (the output of the AV9170 has a small negative phase offset compared to the input).

Early Rush Intergraph cards had a footprint for an oscillator. This would allow clocking the FJR/TMU from that oscillator, instead of the 2D IC.

It was never used, as there is no way to sync that clock to the AT IC. I did test this on an existing card (externally feeding a clock of the same frequency as the AT, but obviously the two clocks are freerunning), and it resulted in:

The later Intergraph revision removes that footprint and adds a regulator. That regulator is present on most late Rush cards, while the early ones (eg. the dual planar ) do not have it.

On early cards, 2D IC/FJR/TMU/etc are powered by 5V. On the later cards with this regulator present, 2D IC/TMU/etc are powered by 5V. The FJR is powered by 5.25V from the regulator.

Regarding clocks, the Rush was probably intended to be clocked much higher, there is a mention of 75MHz is some SDK documentation. However, there is really no signal integrity on the card.

As mentioned earlier, the FJR and 2D IC physically access the same RAM. This means, that while one IC or the other does RAM operations, there are huge stubs because the RAM is also connected to the other IC. To make things works, the BIOS IC also sits on a part of this bus, as well as parts of the VMI connector.

On earlier cards, eg. Hercules Stingray dual planar, the AT3D PCB has two of the RAM address lines are flipped (A0 and A7). On the expansion cards (that hold the 3dfx bits) there are resistors for selecting if it should invert those or not. Obviously they are flipped there as well, as it couldn't work properly if only one of the ICs flipped those.

Usually, swapping address bits is very bad, even for EDO RAM. I tested this on a V2 FBI, inverted two address lines, and the framerate was halved.

I did flip those address lines to the proper position on the Hercules Stingray dual planar card, there was no increase in performance. The card started working properly with the single planar driver though, which it didn't before.

Later single planar cards have all the RAM address lines in the proper order.

Digital video output (eg. HDMI) is not possible on the AT Rush. While the AT25/AT3D has a 16 bit parallel video output bus, some of those bits are multiplexed with the THP bus. 16bpp is not possible in 3D mode. 8bpp would be possible, but it makes little sense.

There are 3 pins, UNK_1, UNK_2, UNK_TP_1. UNK stands for unknown. UNK_1 and UNK_2 have strapping resistors, but I am unsure of the function. UNK_TP_1, on all Rush cards I looked at, is just connected to a test point.

Besides those two pins with strapping resistors, there are 4 more FJR straps that sit on the memory bus:

Their function is currently unknown.

FJR pinout:

Super cool.

This regulator LM317 generates a lot of heat. I add a heatsink for it.
And I always adjust the output voltage of this regulator 5.25-->5.00.
Why this regulator was introduced is a mystery to me. Perhaps, to take some energy from the 12 Volt line. Or maybe, it was planned to increase the clock frequency, for this they raised the voltage a little. There is a desire to remove this regulator and connect the FJR to the 5 Volt line.

It was added there for stability/increasing the clocks a little. Earlier cards, without that regulator, were clocked at 45MHz IIRC.
If it was just for decreasing the load on the 5V PCI line it would have been set to 5V output instead of 5.25V.
You can remove it and just feed the FJR with 5V. If it's stable at 50MHz, just leave it like that.

If it's specifically on 5.25V it feels like either getting more headroom for clocks or compensation for voltage drop over the traces under load. Especially if there is high load on the 5V rail, the 5V from the PCI connector would be anywhere but 5V, so having a precise known voltage is certainly helpful for good results.

Thanks for sharing all that knowledge with us sdz, that's again awesome to dig through!

sdz wrote on 2025-09-02, 09:44:

It was added there for stability/increasing the clocks a little. Earlier cards, without that regulator, were clocked at 45MHz IIRC.
If it was just for decreasing the load on the 5V PCI line it would have been set to 5V output instead of 5.25V.
You can remove it and just feed the FJR with 5V. If it's stable at 50MHz, just leave it like that.

Thanks for your help, this is very useful information.
I have two types of Rush on my desk right now, I measured them:
InnoVision 3DXRush (Alliance) with LM317 - 50 MHz
3Dfx Voodoo Rush A-Trend ATG-2476P (Macronix) without LM317 - 50 MHz

Can you modify the SST96 code in https://github.com/sezero/glide to address the other TMU? I don't know the register interface but it might be that you don't need to modify the driver at all - it might just do bar mapping on behalf of the glide library.