You won’t get any significant benefit from EDO with 486. Sometimes it may lead to even worse performance and this is discussed in this forum.

Generally only the last revisions of the SiS 496 and UM8881 can take any advantage of EDO ram, but with 486s it is best to stick with FPM.

The M919 uses a UM8881f chipset.

Any idea what EDO mode does in the bios? Does it just do faster timings? If that’s the case, then, no, you wouldn’t see a difference if you run both tests with the same bios settings.

What version of the M919 do you have? What Bios are you using?

douglar wrote on 2025-09-20, 11:21:

The M919 uses a UM8881f chipset.

Any idea what EDO mode does in the bios? Does it just do faster timings? If that’s the case, then, no, you wouldn’t see a difference if you run both tests with the same bios settings.

What version of the M919 do you have? What Bios are you using?

V3.4B/F

How to check BIOS version?

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

Anyway, I maxed out to 256MB with two 128MB FPM sticks installed on simm2 and simm4.

CharlieFoxtrot wrote on 2025-09-20, 10:47:

You won’t get any significant benefit from EDO with 486. Sometimes it may lead to even worse performance and this is discussed in this forum.

Generally only the last revisions of the SiS 496 and UM8881 can take any advantage of EDO ram, but with 486s it is best to stick with FPM.

Thanks, at this point I feel very comfortable with the FPM ram equipped with the M919 board.

385387386 wrote on 2025-09-20, 11:36:

to check BIOS version?

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

Anyway, I maxed out to 256MB with two 128MB FPM sticks installed on simm2 and simm4.

It should show a POST string when you boot up. You probably want the 1998 bios. https://theretroweb.com/motherboards/s/pcchips-m919-ver-3.4b

As for the simms, back in the day, all the simms ran on the same lines, so defective chipsets seems less likely. It’s probably isolated to the simm sockets. The M919 boards are very bendy. It’s possible that it flexed and some solder cracked around the simm sockets, or the contacts in the sim socket has some corrosion.

douglar wrote on 2025-09-20, 11:21:

The M919 uses a UM8881f chipset.

Any idea what EDO mode does in the bios? Does it just do faster timings? If that’s the case, then, no, you wouldn’t see a difference if you run both tests with the same bios settings.

What version of the M919 do you have? What Bios are you using?

It doesn’t make much difference even if it is the latest revision, but with those chipsets edo doesn’t tend to decrease performance. The only case where EDO makes any difference with these chipsets is with unusally high number of cache read misses. And even then it isn’t significant, you may see something on benchmarks, but benefits are negligible.

The point is that with 486 EDO is pointless: in the best case scenario you have performance on par with FPM.

douglar wrote on 2025-09-20, 12:22:

385387386 wrote on 2025-09-20, 11:36:

to check BIOS version?

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

Anyway, I maxed out to 256MB with two 128MB FPM sticks installed on simm2 and simm4.

It should show a POST string when you boot up. You probably want the 1998 bios. https://theretroweb.com/motherboards/s/pcchips-m919-ver-3.4b

As for the simms, back in the day, all the simms ran on the same lines, so defective chipsets seems less likely. It’s probably isolated to the simm sockets. The M919 boards are very bendy. It’s possible that it flexed and some solder cracked around the simm sockets, or the contacts in the sim socket has some corrosion.

Thanks answer the mystery. I will try the BIOS from 1998.

Is that the correct version number?

You overclock 486 front side bus to 60/66MHz with EDO memory. That's the main appeal.

The Serpent Rider wrote on 2025-09-20, 12:49:

You overclock 486 front side bus to 60/66MHz with EDO memory. That's the main appeal.

I figured out the 66MHz fsb.

JP3A-A ON
JP3A-B OFF
JP3A-C ON

Weird enough, I initially used Advanced Logic PCI card, the system won't boot at 66MHz fsb. I switch the VGA card with Permedia 2v PCI, the system will boot and stable. How that could happen that Advanced Logic PCI caused the system unbootable? Since the PCI bus running on 33MHz stock speed at 66MHz fsb.

385387386 wrote on 2025-09-20, 11:36:

V3.4B/F […]
Show full quote

douglar wrote on 2025-09-20, 11:21:

The M919 uses a UM8881f chipset.

Any idea what EDO mode does in the bios? Does it just do faster timings? If that’s the case, then, no, you wouldn’t see a difference if you run both tests with the same bios settings.

What version of the M919 do you have? What Bios are you using?

V3.4B/F

How to check BIOS version?

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

Anyway, I maxed out to 256MB with two 128MB FPM sticks installed on simm2 and simm4.

Most likely you can only use all 4 SIMM sockets if every module is single sided. Side 2 of the double sided modules is wired to the same RAS/CAS lines that the odd numbered SIMM sockets are, so you can't use them together

maxtherabbit wrote on 2025-09-20, 13:44:

385387386 wrote on 2025-09-20, 11:36:

V3.4B/F […]
Show full quote

douglar wrote on 2025-09-20, 11:21:

The M919 uses a UM8881f chipset.

Any idea what EDO mode does in the bios? Does it just do faster timings? If that’s the case, then, no, you wouldn’t see a difference if you run both tests with the same bios settings.

What version of the M919 do you have? What Bios are you using?

V3.4B/F

How to check BIOS version?

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

Anyway, I maxed out to 256MB with two 128MB FPM sticks installed on simm2 and simm4.

Most likely you can only use all 4 SIMM sockets if every module is single sided. Side 2 of the double sided modules is wired to the same RAS/CAS lines that the odd numbered SIMM sockets are, so you can't use them together

Maybe, I will try. Thanks.

385387386 wrote on 2025-09-20, 11:36:

The simm1 and simm3 can't work, only simm2 and simm4 can function, why? I tied many 72pin sticks, the result are the same: simm1 and simm3 unworkable. (It seems like PCChips used some defective UMC chips to manufacture the board, does anybody know exactly what issue cause the simm1 and simm3 unworkable?)

The UMC 8881 chipset only has two banks of memory, each with up to four(!) ranks. Typically, the four ranks of a bank are connected to two SIMM slots. If you want to use both slots of one bank, you need to use the same memory type in both of the slots. Any combination is possible: One slot filled with a single-sided SIMM (1 rank used), both slots filled with a single-sided SIMM (2 ranks used), one slot filled with a double-sided SIMM (2 ranks used) or both slots filled with double-sided SIMMs (all 4 ranks used). The UMC 8881 memory controller can use either of the two slots as the "primary slot", which needs to be filled first. It is up to the BIOS to detect which of the two slots of a bank is filled and if only one is filled, to configure the chipset to use that slot as "primary slot".

If only two of the four slots on your board seem to work, this can mean either of two things:

1. Your BIOS does not contain the logic to select which of the two slots is the primary slot, so you need to fill specific slots first.
2. One of the two banks is broken, and the two slots used for that bank don't work.

Furthermore, you can not have more than 128MB per bank, so if you use 128MB SIMMs, each SIMM needs to be in a slot belonging to a different bank.

The UMC8881 has a speed switch option for EDO RAM. It can use EDO RAM at 3-1-1-1 or 4-2-2-2. These timings specifications are comparable to the timing specification of the L2 cache, and they only apply on page hits (EDO is an extended "fast page mode" RAM, it still has the same concept of pages). If I understand that chipset correctly, fast page mode RAM at 0WS also operates at 4-2-2-2, so you wouldn't expect any speed advantage for 4-2-2-2 EDO compared to 0WS FPM. I didn't get 3-1-1-1 EDO to work reliably at anything faster than 33MHz FSB. On the other hand, you can usually get 2-1-1-1 L2 cache at 40MHz FSB, and if you are lucky, also at 50MHz FSB. This means L2 hits generally are faster than L2 misses into EDO RAM at these FSB clock rates. You only have a chance of seeing improvements from using EDO RAM if you have a lot of L2 misses, and you can run EDO at a faster burst than FPM. So EDO might be interesting at 33MHz without L2 cache (3-1-1-1 on L1 misses with EDO, 4-2-2-2 on L1 misses with FPM, but 2-1-1-1 on L1 misses if L2 were present), or at FSB rates sufficiently high that FPM can not keep up at 0WS, so FPM would drop to 5-3-3-3, while EDO might still work at 4-2-2-2. The key point of EDO is that it allows a faster burst speed for RAM chips with the same row access time (that's the "70ns" printed on the chips).

People reporting that EDO only helps at 60MHz FSB made this experience because the "CAS cycle time", which limits the burst speed of 60ns FPM is typically around 40ns, while 60ns EDO is typically around 30ns. 4-2-2-2 at 60MHz uses a cycle time of 32ns. Actually, memory acccess is more complex than just cycle times, but looking at the cycle times that are officially supported suffices to see why EDO performs better at 60MHz than FPM.

I have tested this EXTENSIVELY on the m919, both on v3.4b/f and a v1.5 board

Quality FPM, at 60mhz FSB, will BEAT EDO by exactly 1us if you run cache check from dosbench, or about 1mb/s as measured by other utilities.

The rationale behind this (based on lots of reading about the UMC chipset observations, very simplified) is: there are two ways of using EDO - either natively - like edo, or, in a "workaround" way in FPM mode (this is how the m919 uses it). Now, the tradeoff is - in order for the EDO to be used as FPM a few things need to happen, and this happening creates a 1 cycle penalty (compared to real FPM) while accessing it.

This is a double edged sword however, and it shouldn't be automatically assumed the FPM is in fact better after a certain point. Both me and Feipoa can vow that the extra 1 cycle edo gets delayed by is actually a good thing when running at 60mhz + fsb and thus makes EDO the memory of choice for running high frequencies. It is also much easier to find EDO in higher capacities and faster spec for less $ then quality FPM

For perspective, with a 180mhz amd on 60mhz fsb the difference between FPM and EDO was around 0.2 fps

bertrammatrix wrote on 2025-09-20, 16:40:

I have tested this EXTENSIVELY on the m919, both on v3.4b/f and a v1.5 board

Quality FPM, at 60mhz FSB, will BEAT EDO by exactly 1us if you run cache check from dosbench, or about 1mb/s as measured by other utilities.

The rationale behind this (based on lots of reading about the UMC chipset observations, very simplified) is: there are two ways of using EDO - either natively - like edo, or, in a "workaround" way in FPM mode (this is how the m919 uses it).

In my oppinion, "native" and "workaround" sound more dramatic than the technical difference really is. Most importantly, you would not get better performance from EDO than from FPM in your use case, even if the EDO RAM was used optimally. This is because you are using EDO RAM in a configuration in which "one-cycle operation" (3-1-1-1 EDO mode) is not possible, and your FPM RAM also is fast enough to keep up with "two-cycle operation" (either 4-2-2-2 EDO / 0WS FPM). The difference between 4-2-2-2 EDO and 0WS FPM is indeed the extra clock required to "shut down" the output of EDO RAM at the end of the cycle, so 4-2-2-2 EDO is slightly slower than 0WS FPM, just as you described.

If the chipset would be able to control the /OE pin of the EDO RAM, it could shave off the extra cycle required to "shut down" the EDO RAM output driver (you might call this "native mode"), but it would not make EDO faster than FPM, just get "on par" with FPM. There is no "native mode" that unlocks higher performance. EDO is only faster than FPM if you are able to sustain a higher burst rate because of the faster "/CAS cycle time" aka "Page-Mode cycle time". If your FPM keeps up with EDO, you have really fast FPM that can deal with the 33ns cycle time produced by the 8881 chipset at 60MHz in 0WS mode. EDO would only be able to beat FPM if you get EDO SIMMs that work at 16ns cycle time (required by the 3-1-1-1 EDO mode). There are EDO chips that fast, mainly used on the first generation of 3D-capable graphics cards (e.g. 3Dfx Voodoo, S3 Virge/DX), but oftentimes, those chips are just 256k * 16 Bit, so you could build single-sided 1MB SIMMs or double-sided 2MB SIMMs out of them. Well, this makes me wonder whether I should actually try mounting some of the ultra-fast EDO chips on old low-capacity PS/2 modules and test whether I can get them to work at 3-1-1-1 EDO.

bertrammatrix wrote on 2025-09-20, 16:40:

It is also much easier to find EDO in higher capacities and faster spec for less $ then quality FPM

This is clearly the case. Furthermore, even at the same /RAS access time specification, EDO is more likely to run stable at 33ns cycle time than FPM, so less cherry-picking (or "musical chairs") required to select modules that work reliably at FSB60.

bertrammatrix wrote on 2025-09-20, 16:40:

Both me and Feipoa can vow that the extra 1 cycle edo gets delayed by is actually a good thing when running at 60mhz + fsb

I wonder what upside you get from the delay by one clock. Can you elaborate why "it is a good thing"? I can definitely understand "it is not worth the trouble trying to find big fast FPM RAM that works at 0WS at 60MHz, as the 1-cycle performance hit is typically negligible", actually, I tend to agree with that statemend. I can't imagine anything that works better with that delay than without that delay.

mkarcher wrote on 2025-09-20, 17:29:

In my oppinion, "native" and "workaround" sound more dramatic than the technical difference really is. Most importantly, you would not get better performance from EDO than from FPM in your use case, even if the EDO RAM was used optimally. This is because you are using EDO RAM in a configuration in which "one-cycle operation" (3-1-1-1 EDO mode) is not possible, and your FPM RAM also is fast enough to keep up with "two-cycle operation" (either 4-2-2-2 EDO / 0WS FPM). The difference between 4-2-2-2 EDO and 0WS FPM is indeed the extra clock required to "shut down" the output of EDO RAM at the end of the cycle, so 4-2-2-2 EDO is slightly slower than 0WS FPM, just as you described.

Taking into account the fake write cycle to tristate the EDO RAM,
would it be accurate to call these,
3-1-1-2 (EDO-enabled)
4-2-2-2 (FPM 0 W/S)
4-2-2-3 (EDO-tolerant 0 W/S)

We haven't talked about whether Pentium chipsets have to do this fake write cycle to shut off the EDO--looking at 430HX datasheet, having a dedicated MD[63:0] I suppose not?

However I know you and I have talked about this before--the motivations of adding EDO to late 486 chipsets. EDO-enabled mode would be for L2-cacheless designs, while EDO-tolerant would allow budget 486 systems to survive as the price of EDO DRAM dropped below FPM (similar to how the price of DDR_n drops below the price of DDR_n-1 as one generation supersedes the prior). Bus speeds over 33 MHz were also arguably uninteresting while they were making this decision, since they would be targeting DX4-100 and Am5x86-133 most likely, and an OEM would want to target 3-1-1-1 mode while designing those 1996 486 systems to compete with the Pentium 75s.

jakethompson1 wrote on 2025-09-20, 17:56:

Taking into account the fake write cycle to tristate the EDO RAM, would it be accurate to call these, 3-1-1-2 (EDO-enabled) 4-2- […]
Show full quote

Taking into account the fake write cycle to tristate the EDO RAM,
would it be accurate to call these,
3-1-1-2 (EDO-enabled)
4-2-2-2 (FPM 0 W/S)
4-2-2-3 (EDO-tolerant 0 W/S)

EDO-enabled versus EDO-tolerant still sounds like "EDO-enabled" does something fundamentally different to "EDO-tolerant" except for using twice the burst rate. I would prefer a terminology like

suggestion wrote:

3-1-1-2 (EDO-compatible -1 W/S)
4-2-2-2 (FPM-only 0 W/S)
4-2-2-3 (EDO-compatible 0 W/S)

jakethompson1 wrote on 2025-09-20, 17:56:

We haven't talked about whether Pentium chipsets have to do this fake write cycle to shut off the EDO--looking at 430HX datasheet, having a dedicated MD[63:0] I suppose not?

Any chipset working with PS/2 EDO SIMMs might have to do it. While dedicated memory pins avoid that the memory output drivers disturb the front-side bus, you still have the memory data pins of multiple ranks connected in parallel, and unless the chipset decides to only ever keep one rank open, it still has to keep non-addressed ranks with their page still open from driving the data bus. There are two ways to prevent that a rank with an open page drives the memory data bus: Either you do the false write start thing (which costs one cycle), or you de-assert /OE on the EDO chips. It's too bad the PS/2 SIMMs do not expose /OE, so doing a false write start is (as I understand it) the only option. Rumor has it that the Intel chipsets beat the competition by having a better strategy to decide what pages (plural!) to keep open and what pages to close in RAM, reducing page-miss delays. The tradeoff is that keeping a page open makes page hits faster, but makes page misses slower at the same time, because at a page miss, you still need to close the still-open page (takes the RAS precharge time) before you may open the new page (takes approximately the RAS-to-CAS delay before the access can continue like it would be performed on a page it). So keeping a page open for some time (while you expect that you might get a page hit in that rank) is usually a good idea, but so is closing the page if so much time has passed that you expect the next access in that rank is likely unrelated to the page still open.

jakethompson1 wrote on 2025-09-20, 17:56:

However I know you and I have talked about this before--the motivations of adding EDO to late 486 chipsets. EDO-enabled mode would be for L2-cacheless designs, while EDO-tolerant would allow budget 486 systems to survive as the price of EDO DRAM dropped below FPM (similar to how the price of DDR_n drops below the price of DDR_n-1 as one generation supersedes the prior). Bus speeds over 33 MHz were also arguably uninteresting while they were making this decision, since they would be targeting DX4-100 and Am5x86-133 most likely, and an OEM would want to target 3-1-1-1 mode while designing those 1996 486 systems to compete with the Pentium 75s.

While cache-less 486 is the prime target for 3-1-1-2 EDO, even with L2 cache you should be able to run 3-1-1-2 with EDO at 33MHz (I failed to get that rate at FSB40 in the notorious thread 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2)), which still is a win compared to 4-2-2-2 non-EDO-compatible FPM on cache misses with no downside. If the 486 performance chasers were not completely ignoring FSB33, I would expect EDO to have a better reputation. The 486 performance chasers are not wrong to ignore FSB33, though. The highest multiplier you can get on an Am5x86 (aka DX5) is *4, and FSB33 would limit you to 133 MHz internal clock, which is pointless, as most 5x86 processors overclock perfectly fine to 3*50 and 4*40 MHz, which will generally yield better performance than 133MHz.

Well, re-reading the thread, strike that. At least with 3-1-1-1 SRAM timing, you don't seem to get 3-1-1-2 EDO reads even if configured, as feipoa measured in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply) - but I don't think anyone already tested whether 3-1-1-2 EDO timings kicks in at 2-1-1-1 SRAM timing.