Maybe the chipset uses 64 bit wide banks. While this is the norm on Pentium chipsets, 64 bit wide memory access (or permanently enabled bank interleave) is also used by some high-performance 486 chipsets, that want to transfer a 486 cache line within 2 memory cycles. The Intel 430 series (e.g. Saturn) is an example of this architecture.

Even without combining two modules into a virtual 64-bit module, you can access 4 double-sided modules (8 ranks) with just 4 RAS lines if you have sufficiently many CAS lines. A rank is only active on the data bus if it receives both RAS and CAS, so module multiplexing can be done using either RAS or CAS or a combination of both. Using only RAS for module selection is preferable both from a performance point of view and from a power management point of view, so that's why this scheme is most common.

I've just seen you other post in the UMC8881/8886 thread. For that chipset, the answer is indeed that it has 8 CAS lines, see Re: UMC8881/8886 Datasheet .

mkarcher wrote on 2025-10-28, 17:32:

Maybe the chipset uses 64 bit wide banks. While this is the norm on Pentium chipsets, 64 bit wide memory access (or permanently enabled bank interleave) is also used by some high-performance 486 chipsets, that want to transfer a 486 cache line within 2 memory cycles. The Intel 430 series (e.g. Saturn) is an example of this architecture.

Even without combining two modules into a virtual 64-bit module, you can access 4 double-sided modules (8 ranks) with just 4 RAS lines if you have sufficiently many CAS lines. A rank is only active on the data bus if it receives both RAS and CAS, so module multiplexing can be done using either RAS or CAS or a combination of both. Using only RAS for module selection is preferable both from a performance point of view and from a power management point of view, so that's why this scheme is most common.

so is it possible to using 4 RAS 4 CAS to drive 32M*4? does this need additional logic circuit? do you know the logic of each signal? if 4bank only, we need to using 64MB simm 72, it's possible using 4MB*4bit chip to made this 64MB RAM?

youxiaojie wrote on 2025-10-29, 02:42:

so is it possible to using 4 RAS 4 CAS to drive 32M*4? does this need additional logic circuit? do you know the logic of each signal? if 4bank only, we need to using 64MB simm 72, it's possible using 4MB*4bit chip to made this 64MB RAM?

No, 4 RAS, 4 CAS is unable to drive 8 ranks of 32 bits. 8 RAS, 4 CAS (e.g. on the SiS 496) or 4 RAS, 8 CAS (e.g. on the UMC8881) is required instead. If you use 4M * 4mbit chips, a rank (a "rank" is what is connected to the same RAS line and the same set of CAS lines) will have 4mega-entries. For a 32-bit bank, that would be 4 mega-entries of 4 bytes, which is 16 megabytes. 64MB SIMMs are made of 16M*something chips, most often 16M*1 or 16M*4.

With extra circuit logic (usually implemented in a PAL), you can emulate 16M*4 using four 4M*4 chips.

youxiaojie wrote on 2025-10-28, 15:24:

I see there's some board support 4*32M doubleside 72 simm, but the chipset seems only have 4 ras how do they achieve it? or the chipset have 8ras?

BTW what board are you talking about?

Some FinALI 486 mobos have 4 slots, but support only single sided SIMMs.