Marco wrote on 2025-11-04, 11:35:
I wonder whether there are any IDE ISA controllers that support busmaster DMA.
Sorry for starting with a focus on a technicality, but it will be relevant for this reply. The typical ISA IDE adapter card is not worth to be called a "controller", because it doesn't do anything except for forwarding ISA signals to the IDE cable. The hard drive controller is integrated into the drive instead of being on a controller board (thus the name "integrated drive electronics" for IDE). So for ISA, we are usually looking at brain-dead IDE ISA interface boards.
Marco wrote on 2025-11-04, 11:35:
This card is still an ISA IDE interface card without logic on this card. This card is special in that it allows 4 channels to be connected (instead of the single channel at fixed address 1F0 and IRQ14, used by stanard ISA IDE interface cards), and it does not only forward the lines required for port IO from the ISA bus to the drive, but it can also forward a DRQ/DACK of the ISA bus to the drive. Most ISA IDE interface cards do not connect anything to the single DACK/DRQ pair on the IDE cable. So this is indeed third-party DMA driven by a 8237-like DMA controller.
Many IDE drives implement ISA-compatible DMA: The protocol of single-word DMA is identical to ISA DMA in "single cycle mode", and the protocol of multi-word DMA is identical to ISA DMA in "demand mode". The data rates are low, if a 8237 at 4MHz is driving the stuff. With an interface card like the GSI 4c, you will likely not get great performance unless you can run the ISA DMA controller at 8MHz instead of 4MHz.
Marco wrote on 2025-11-04, 11:35:
The manual of this card can be found at http://www.bitsavers.org/pdf/siig/SIIG_CI-105 … nual_199505.pdf
The quote "up to 8.33MB/s" sounds like bus-master DMA. You only get that rate at 16-bit transfers if every transfer uses just 2 ISA bus clocks. The 8237-type DMA cycles take 4 clocks, there is a compressed mode, which AFAIK is not used in PC/AT-type system that can get down to 3 clocks, but it cleary can't get to two clocks. Also, third-party DMA at 8 or 8.3MHz is out of spec. Chapter 4 in that manual shows the IDE connector pinout, and it misses the DMA pins (DRQ on 21, DACK on 29) which might be worrysome, but as the manual does not stop pointing it it uses "Multiword DMA", I suppose it is just a lazy pinout diagram copied from some source that doesn't implement DMA.
I can't find any pictures of the card that would allow me to reverse engineer it sufficiently far to find out whether it might be able to implement bus mastering.