I saw some chips support 486 and 386 as well. is It possible to make a interposer to glue 386 387 in a pcb act as 486dx to use in 486 motherboard?
It might be possible, but you'd need extra logic to handle cache coherence (a 386 would have only one level of cache if present on the motherboard) and signals to an external math coprocessor.
It would be easier (and cheaper) to source a motherboard with 386, 387, and 486 sockets.
3 separate sockets is rare, they often have one socket doubled up, or skip 387 capability.
Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.
BitWrangler wrote on Today, 03:44:3 separate sockets is rare, they often have one socket doubled up, or skip 387 capability.
I think the OP is talking about making a drop in replacement for a 486 out of a 386 and 387 on a daughter board.
I’m not sure the FPU is required to replace a 486. The on chip cache on the otherhand is the real story.
386+387 combo is never going to fully replace 486 because:
- 386 can't do alignment control, although that's very rarely used feature
- 386 paging WP bit doesn't protect ring 0 pages, this was "fixed" in 486 and requires an extra CR bit to be set, protected mode OS kernels started using and then require that feature (thus dropping 386 support)
- 386 can't report FPU errors via internal exception and requires the slower IRQ method
- 386 can't BSWAP or CMPXCHG, which is also a requirement for more modern OS kernels
Now these are "mostly software" issues. From HW standpoint there is lack of internal cache and coherency protocol (as well as burst mode) but I suppose it's not such a big deal since 486 can disable its internal cache and mostly run like 386. It would not take a lot of glue logic to make that work. However the 486 expects to see data presented on different I/O pins in case of split or smaller than 32-bit data transfers. This is where chipset comes in and translates narrow busses to what the CPU requires. The 386 also lacks BS8 signal so if the mobo is using that (for say, BIOS ROM access) that has to worked around on the interposer.
Frankly the amount of glue logic required to make the bus look like 486 with 386 chip would be such that the design would be very limited in max frequency. Possibly way below the usual 33MHz because some chipset timings might just be making it so any further delays would break it, or require wait states on everything. The software part... I'd argue it'd be easier to fully implement the 386 core with glue logic hacks entiretly in FPGA rather then using a true 386 chip. At this point one might just implement 486 core, including an FPU.
