Here is the result of the UMC Testing. Curiously, the UM82C871F with the manual timing settings got the fastest scores, even though it's older. I just did benchmarks, I didn't do any long term reliability tests to see if I could run at the selected speeds without corrupting the data.

Here are my test cards--
UM82C871F - https://theretroweb.com/expansioncards/s/sili … nc-old-name-abi
UM85C418F -- https://theretroweb.com/expansioncards/s/gain … d-cardex-vl-1av
UM8672F - https://theretroweb.com/expansioncards/s/unkn … 3295umv-a-ver-1

Notes:

• I had to increase the timing on the UM85C418F to get the SD-IDE bridge to work reliably
• Even on the most relaxed timings, the UM85C418F would constantly return an incorrect geometry in some cases.
• The UM85C418F driver, XUB & MrBios (when enabled) supported block mode transfers with the LiteOn Msata device and showed performance improvements
• When using XUB with no additional drivers, speedsys would skip the write test on the bridged msata device, no info message given
• I dropped the UMC bios testing. It wasn't producing very interesting results and it was making the result chart confusing

douglar wrote on 2023-05-10, 00:12:

I uploaded a bunch more drivers today--

Winbond W83759AF Config Utility with Source Code -- Anytime there is source code, it gets interesting

Looking in the source code I see only W83757AF mentioned. Not W83759AF. As far as I know those chips are not compatible so the source code will probably not work on a W83759AF.

I see them on The Retro Web as well: https://theretroweb.com/chips/6574 but even the file name says W83757AF not W83759AF.

Yoghoo wrote on 2026-01-04, 10:21:

Looking in the source code I see only W83757AF mentioned. Not W83759AF. As far as I know those chips are not compatible so the source code will probably not work on a W83759AF.

I see them on The Retro Web as well: https://theretroweb.com/chips/6574 but even the file name says W83757AF not W83759AF.

Thanks for pointing that out. I adjusted things to make more sense

I saw a number of failures in my last set of benchmarks when I tried to push the IDE timing to the limit. I started researching what & why is going on when VLB IDE transfers go wrong and I found things I didn't expect.

I had always assumed that faster PIO modes were just faster PIO modes. It seems that it was pretty much true for PIO0-->PIO1-->PIO2 but beginning with PIO3 and definitely with PIO4, things changed. The ATA2 PIO modes have complicating factors.

Here's what I learned-- Please let me know if I'm off base here--

• The timing for PIO3 on VLB is tight and for PIO4 it is very tight. Some VLB chips have internal strobes to generate their own PATA clocks. Some VLB chips have internal buffers. Chips with internal strobes & buffers tend to be more reliable as the timing gets tighter.
• Sometimes faster 486 computers ( > 66Mhz ) have increased difficulty with faster PIO modes compared to slower 486 chips (<=66Mhz ) because the slower CPUs ran the driver code more slowly, and introduce extra waits that help when signals from an IDE device arrive little slow. When > 100 Mhz chips came out in 1994, not all systems that were validated at 33Mhz continued to work, because the CPU started sampling before the controller had the data ready.
• A properly implemented IORDY (IOCHRDY) signal allows the faster CPUs to be reliable because it allows the IDE device to tell the controller that the data will be arriving a few ns late, but not all vendors implemented IORDY the same way.
• Some VLB IDE controllers don't provide IORDY in a way that slower 486 CPUs can handle with 100% reliability, and in this edge case, the slower CPU's were less reliable. Perhaps this is why so many cards provide a way to disable IORDY.
• The actual performance of PIO4 operation is very often only marginally better than PIO3 because the IDE device asserts a lot of IORDY waits or the driver is slower because of how IORDY was implemented.
• As far as I know, all solid state storage expects a functioning IORDY, even though they are usually able to handle PIO3 without it. I guess there is a chance that cheap PATA-SATA bridges could fumble the IORDY signal.

Now trying to figure out which chip did what is harder, because there's not a lot of documentation.

These chips seem to have PIO4 support

• Promise (20x30x)
• SiS 83C601
• ADI/2 (Adaptec/ALi/Appian)
• Winbond (W83759AF)
• CMD PCI0640B
• QDI Vision 6580
• Atronics (IDE-2015PL)
• GM82C712

Interesting stuff, I was always wondering why PIO mode 2 drives seem to behave nicer than "better" PIO mode 2 and 4 drives on high clocked VLB controllers.

douglar wrote on 2026-01-02, 13:58:

Here is the result of the UMC Testing. Curiously, the UM82C871F with the manual timing settings got the fastest scores, even th […]
Show full quote

Here is the result of the UMC Testing. Curiously, the UM82C871F with the manual timing settings got the fastest scores, even though it's older. I just did benchmarks, I didn't do any long term reliability tests to see if I could run at the selected speeds without corrupting the data.

The attachment Untitled.png is no longer available

Here are my test cards--
UM82C871F - https://theretroweb.com/expansioncards/s/sili … nc-old-name-abi
UM85C418F -- https://theretroweb.com/expansioncards/s/gain … d-cardex-vl-1av
UM8672F - https://theretroweb.com/expansioncards/s/unkn … 3295umv-a-ver-1

Notes:

• I had to increase the timing on the UM85C418F to get the SD-IDE bridge to work reliably
• Even on the most relaxed timings, the UM85C418F would constantly return an incorrect geometry in some cases.
• The UM85C418F driver, XUB & MrBios (when enabled) supported block mode transfers with the LiteOn Msata device and showed performance improvements
• When using XUB with no additional drivers, speedsys would skip the write test on the bridged msata device, no info message given
• I dropped the UMC bios testing. It wasn't producing very interesting results and it was making the result chart confusing

Today i test my UM8672F VLB with 40MHz VLB bus speed and get up to 5100 KB/s in SPEEDSYS

Babasha wrote on 2026-01-06, 20:34:

Today i test my UM8672F VLB with 40MHz VLB bus speed and get up to 5100 KB/s in SPEEDSYS

Nice!

Any reason why you are not looking at pci solutions that support DMA? It does make Windows more pleasant.

douglar wrote on 2026-01-07, 02:11:

Babasha wrote on 2026-01-06, 20:34:

Today i test my UM8672F VLB with 40MHz VLB bus speed and get up to 5100 KB/s in SPEEDSYS

Nice!

Any reason why you are not looking at pci solutions that support DMA? It does make Windows more pleasant.

Yeap! There is ONE BIG REASON)))
I love strange, unknown, unbelivable hardware with lost manuals, drivers, info

Babasha wrote on 2026-01-07, 05:38:

Yeap! There is ONE BIG REASON)))
I love strange, unknown, unbelivable hardware with lost manuals, drivers, info

Then you are on target here. If you are looking for a lack of documentation, UMC is the way to go!

Here is the source code to the Legacy Linux driver if you want to go a-hackin'.

https://chromium.googlesource.com/chromiumos/ … s/ide/umc8672.c

Edit -- Looking through that source code, I see that author assumed that Speed 11 = PIO4. Didn't match my testing. Speed 11 matched PIO2 in my testing and according to the driver, speed 11 uses the smallest possible values in the timing registers: 1 / 1 / 0

I saw hints that there was a modded driver that allows PIO4. Not sure how to get there unless the dos driver I'm using has different values in it's speed table. Something to check out later today.