I'd say the bus speed jumpers are glitchy or the clockgen has taken a shit and you're running a 50mhz bus.

It appears that the board doesn’t like SDRAM. Just installed 2x16MB EDO RAM and the CPU runs at 233 MHz again…weird but oh well.

I always ran EDO than SDRAM on those combo boards.
Early SDRAM was a marginal improvement over EDO and EDO supported higher capacity than SDRAM.
It's good to see the tech exists today reminds when it was in it's day on dialup and Windows 98.

Did you set JP2 for 3.3V operation with SDRAM?

Have you tried using just one DIMM in either slot to see if it boots up properly?

@Beerfloat: no and no.
Now I’m tempted to give it another try but then I’d need to remove the board again. Those SDRAM modules took alot of force to install.
So what zapbuzz is saying, not much of an improvement and I’m using this machine for DOS only. No need for 64MB of RAM anyway.

Kouwes wrote on 2026-01-06, 17:48:

@Beerfloat: no and no.
Now I’m tempted to give it another try but then I’d need to remove the board again.

It's kinda what we do around these parts haha.

The trying IS the fun 😉

Kouwes wrote on 2026-01-06, 16:21:

It appears that the board doesn’t like SDRAM.

I had a very similar issue on my K7S5A. Despite the mediocre reputation of that cheap board, I personally did not have any issues yet that are clearly due to board quality problems. In my case, the SPD EEPROM on one of my DIMMs was bad and blocked the I2C bus that is used to read the SPD EEPROMs. The clock generator is connected to the same I2C bus, so the BIOS also was unable to communicate with the clock generator, which had it stick to its default bootup frequency. In case of the K7S5A, the default bootup frequency is 66MHz, while the officially supported FSB frequencies are 100MHz and 133MHz (the BIOS reconfigures the clock generator to either of these frequencies during the POST). With the broken DIMM, the Athlon XP 2200+ (1800MHz) was running at 900MHz instead of 1800MHz (it's an FSB133 processor).

Yes I was wondering if there was something it didn't like about the SPD ... also thinking it maybe saw fast timings on a later module and went "Psshaw, that's not possible, Ima set it safe as safe can be."