DistWave wrote on 2023-06-28, 17:07:
Only issue is the floppy drive, it doesn't read floppy disks when cache is enabled (DMA and no cache flush is a know source of issues).
Cyrix/TI 486SLC/DLC and TI 486SXLC/SXL can be configured to flush cache any time HOLD signal goes active, which typically indicates that another bus master, e.g., DMA controller, would like to have control of the bus (and can potentially update the memory). The HOLD signal is already wired in all 386SX motherboards, so all you need to do is to enable "BARB" feature. It is done by setting bit 5 in the CCR0 register. I think there are tools around (cache486 or similar?) that would do that. It can also be done very easily with a short assembly program:
MOV AL,0C0h
OUT 22h,AL ; select CCR0
IN 23h,AL ; read the current CCR0 value to AL
OR AL,20h ; set bit 5
MOV AH,AL ; temporarily store AL to AH
MOV AL,0C0h
OUT 22h,AL ; select CCR0
MOV AL,AH ; restore AL from AH
OUT 23h,AL ; write new value to CCR0
INT 20h; exit to DOS
You can even type that using DOS DEBUG and save it as .COM file...
Also, earlier in the thread there is a confusion about A20M line. I think it wouldn't matter in most cases, except if you're using some weird applications from the early DOS era...
The explanation is a bit of trip to the PC history... The 8086/8088 had 20 bit physical address, which was generated using two 16 bit values: segment and offset, something like: physical_address = segment * 16 + offset. As one can notice, it is possible to generate addresses larger than 1 MiB (e.g., if you set segment to 0FFFFh, and offset larger than 16). In the 8086/8088 the address will simply roll over, and the first 64 KiB of memory will be accessed.
Some creative folks found it to be useful to do tricks and used this mis-feature... Most notably, MS-DOS itself uses it to emulate CP/M style calls using JMP 5 instruction...
A few years later Intel came up with 80286, and a few years after 80386, and so on... All these processors had more than 20 address lines and were able to address more than 1 Mib of memory. And if one would employ the abovementioned trick, instead of rolling over, the processor would access the memory above 1 MiB, which caused incompatibility... IBM "fixed" the issue by connecting the CPU A20 address line to the memory through an AND gate, with the other input of the AND gate connected to the keyboard controller (A20 GATE). So that A20 line can be connected to the memory or forced to '0' by issuing a command to that keyboard controller. (It seems like IBM really enjoyed having a microcontroller in the IBM AT design. They also used that to do a software controlled reset for the 80286 CPU).
When the CPUs with integrated cache entered the picture. Flipping the A20 GATE changes the memory mapping, and the CPU knows nothing about it... So Cyrix/TI CPUs implemented the A20M input. Any time the state of that input changes, the CPU flushes the cache lines that are mapped to the first 64 KiB at each 1 MiB boundary. From hardware perspective it means that A20M line needs to be wired to the keyboard controller (typically pin 22 for the DIP-40 keyboard controllers or pin 25 for the PLCC-44 keyboard controllers).
If for some reason you cannot do this hardware modification, it is also possible to set the bit #0 of the CCR0 to '1', which will disable caching of the first 64 KiB at each 1 MiB boundary. This will result in some performance degradation.
