Hi red-ray,
unfortunately I don't have access to my K6-3 machine for a while from sunday on, so be patient with test requests after saturday.
However, on my other place I have a 486 with 256 MB of RAM where I easily can simulate a similar situation.
My machine is a K6-3 400 MHz on an old 430TX based QDI Titanium IB+. It has installed its maximum of 256 MB RAM.
The K6-3 has an internal on-die 32 kB L1-D, 32 kB L1-I and 256 kB L2 cache.
The QDI Titanium IB+ has 512 kB external cache, which is L3 when using a K6-3, K6-2+ or K6-3+ and L2 when using a K6 or K6-2.
The 430TX chipset has limited cacheable area of 64 MB when paired with 512 kB of external cache.
That cacheable area limit means that megabytes 0-63 are covered by external cache.
But megabytes 64-255 are not covered by external cache.
This means there is a difference on where you place your memory area for doing the cache latency tests.
If you use automatic placement, it depends on the operating system where that memory area will be located.
A 9x based Windows allocates memory requests bottom-up, so it is most likely inside the cacheable area of my machine.
A NT based Windows allocates memory requests top-down, so it is most likely outside the cacheable area of my machine.
So it is clear that there are almost no differences on my screenshot in the area 384 kB and 512 kB to the higher areas and it won't be listed there.
If you fix this I would see differences in the 384 kB and 512 kB area.
Which machines may be affected? All machines with on-board cache, so all 386, 486 and Socket 5, Socket 7 and SS7 boards. Pentium Pro, Pentium II, Athlon and better machines are not affected*.
*As far as I remember there may be some CPU models with internal L2 cache that do not cover full RAM, like not all of the 4 or 64 GB.
The [Cache-o Latency] screenshot does not show the effect of my external L3-cache in the 384 and 512 kB area inside the cacheable area.
The [Machine] screenshot shows that internal L2 is not shown on this screen but the external cache is declared as L2 although it is a L3 here in fact.
It also shows some weird "K5" and "K6 400".
Memory information shows all 4 ranks of my 2 128 MB DIMMs, that are 2 ranks on each DIMM. You display it as 4 "banks". (HWinfo does the same)
It also does not show the devices in the PCI slots. Perhaps it gets confused by the PCI-to-AGP bridge on my Matrox G450 PCI. (HWinfo does the same)
-- Edit:
Debug output files here: Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing
I have to edit this post again. All what I said about memory allocation differences probably is just for the kernel memory allocation.