No hardware resources estimation shown in readme.md and no performance indicators given.
As I understood the output is produced in simulation only. The implementation could be a fully functional model which either will not fit in available fpga boards (like MiSTer), or will choke because of limited memory throughput and high latencies.
Still cool though, would be great if he redesigned the inner pipeline with the modern memories in mind - high throughput, high latency. It's always the memory bandwidth that limits the possibilities.

vstrakh wrote on Today, 07:02:

No hardware resources estimation shown in readme.md and no performance indicators given.
As I understood the output is produced in simulation only. The implementation could be a fully functional model which either will not fit in available fpga boards (like MiSTer), or will choke because of limited memory throughput and high latencies.
Still cool though, would be great if he redesigned the inner pipeline with the modern memories in mind - high throughput, high latency. It's always the memory bandwidth that limits the possibilities.

The designer said on reddit that initially with a DE-10 nano he was only able to get 12.5Mhz cycle accurate, but since optimised it to achieve 50Mhz which should be the same as an original Voodoo. I imagine there still much room to improve.

Why then no stats are listed in the repository?

Also, normally it's not "much room to improve" but "too much stuff doesn't fit timings and has to be redesigned from scratch".
I'm skeptical about SpinalHDL use. While it allows you to think on the level farther from the underlying hardware, squeezing the last drop of performance in tight constraints comes from relying on that hardware architecture, planning with the available hw blocks properties and their relative layout on the chip.

vstrakh wrote on Today, 08:17:

Why then no stats are listed in the repository?

They are available on reddit for you to get answers to anything you need, I obviously don't know

https://www.reddit.com/r/FPGA/comments/1s18vi … on_of_the_3dfx/

Hi! Creator here. Regarding the architecture, the Voodoo is pretty much a giant linear pipeline so there's plenty of opportunity for retiming beyond the 50 Mhz I am sitting at right now. SpinalHDL makes retiming way easier than Verilog or VHDL and gives you just as much control.

I believe the main risk right now is the memory interface. I explicitly designed it so that you can plug it in to almost anything, including a single modern DDR interface. That does mean I need fillbuffers for framebuffer access and a cache for the texture unit in order to guarantee speed with bursty accesses. If you were to use separate single-cycle memories for the framebuffer and textures like the original Voodoo then you should be able to get to the theoretical 50 Mtx/s fairly easily with this design.

That's exactly what I'm working on right now. Tomb Raider is at 5 FPS on the DE-10 because of general memory contention issues. But I have plenty of ideas still. Give me a couple weeks and hopefully it is running at full speed.