Any clues at the usual suspects, minuszerodegrees, ardent tool, OS/2 museum ??

I couldnt find any diagrams, and only couple worse quality pictures.

Pages with more pics FWIW...

https://wiki.preterhuman.net/IBM_Personal_Sys … Display_Adapter
https://www.vgamuseum.info/index.php/componen … display-adapter

Great quality, but sadly 4 layer board with signals on second layer 🙁

In theory, by direct clue or induction, the answer is buried somewhere in The PS/2 graphics subsystems technical reference, if the board is indeed just a standalone implementation of the early onboard PS/2 VGA.

Operational principles of EGA/VGA are known, so is EGA implementation thru IBMs original diagrams and even Tube Times fantastic reversed pcb https://github.com/schlae/EGACard.
Original EGA did in fact use two LSI GDCs (Graphics Data Controllers) each controlling 4 ram chips and 16bit of data bus giving it combined 32bit data bus.

What I got curious about is IBMs first standalone VGA implementation. I was wondering if IBM simply consolidated CRT Controller (CRTC), Timing Sequencer (TS), Attribute Controller (ATC) and two GDCs into one huge ass ~200 pin LSI and called it a day or if they tried some clever optimizations like narrower bus and running ram at twice the clock etc.

Now that I sat on this a few days I think they just shrank and integrated original design and ram is indeed wired just like in EGA.

I have the original IBM VGA adapter. Some friendly person from vcf forums sold theirs to me for a generous few hundred dollars of compensation, when I was developing CRT Terminator, so that I was able to verify the original specification behavior.

Uploaded closeup photos of the card now to https://oummg.com/manual/imgs/IBM_VGA_75X9017XM/closeup/

Also ran my multimeter on the RAM chips. I got somehow odd asymmetric results, not sure what to make of it. See the last photo in the above link. Pins marked with the same letter represent multimeter beeping connectivity. Unmarked pins did not beep connectivity with any other pins.

Let me know if that helps, and if there are some multimeter test points you'd still like to know.

Wow thank you!
Damn I was at peace with my assumptions, now I verified some and it doesnt match with reality 😐

What is ok:
B - +5V
A - common OE/G
C - common WE
X - common CAS on [U9 U16] bank
WSRPN - common A0 A1 A2 A3 A7 on two banks
Y - common CAS on [U22 U29] bank
VUTQO - common A0 A1 A2 A3 A7 on two banks

but:

L M not linked is definitely wrong, both are Ground so there is no way those would not be connected.
GIJ A6 A5 A4 not linked with F H K second set of A6 A5 A4 also looks wrong, especially after reversing what could be glanced from pictures

kicad project with partial RE https://github.com/raszpl/OG_VGA_ram_layout

Those not connected grounds make me thing you lost count during measurements? 🙁 😀
Could you recheck U16 pins 6 7 8 lack of connection to U22 6 7 8? Looking at tracks there are clear signs those are connected under U16.
Second weird thing unrelated to your measurements is CAS on the other two banks. It sure looks like banks are every second chip for some reason with U8 U 28 one bank and U15 U21 second one. Weird.
is U15 pin 16 connected to U21 pin 16? and U28 16 to U8 16?
is U8 5 connected to U28 5? That would mean its going over two VIAs to get there.
are pins 6 7 8 linked between U8 U15 U21 U28?

Lastly it looks suspiciously like the data bus might be connected between banks making it NOT one 32bit wide pool 😮
Could you please buzz out pins 2 4 15 17 if any are connected between banks?

IBM had to have some problems with signal integrity to slap those resistor network termination all over the place on such a small 4 layer board 😮 Naughty engineer routed on ground layer and paid the price.

Thanks, really good pointers.

rasz_pl wrote on 2026-05-19, 20:57:

L M not linked is definitely wrong, both are Ground so there is no way those would not be connected.

You are absolutely right here, indeed when I re-check, L and M are all connected.

rasz_pl wrote on 2026-05-19, 20:57:

GIJ A6 A5 A4 not linked with F H K second set of A6 A5 A4 also looks wrong, especially after reversing what could be glanced from pictures

Also correct here!

rasz_pl wrote on 2026-05-19, 20:57:

Could you recheck U16 pins 6 7 8 lack of connection to U22 6 7 8? Looking at tracks there are clear signs those are connected under U16.

At this point I got to realize that the reason I missed these is that the speaker on my multimeter is acting up and doesn't always buzz... visually verifying the resistances on screen confirms that U16 pins 6 7 8 are connected to U22 6 7 8. Zero ohms.

rasz_pl wrote on 2026-05-19, 20:57:

Second weird thing unrelated to your measurements is CAS on the other two banks. It sure looks like banks are every second chip for some reason with U8 U 28 one bank and U15 U21 second one. Weird.
is U15 pin 16 connected to U21 pin 16? and U28 16 to U8 16?

Yes, correct to both. Updated the diagram with α and β (ran out of letters)

rasz_pl wrote on 2026-05-19, 20:57:

is U8 5 connected to U28 5? That would mean its going over two VIAs to get there.

Yes it is, zero ohms again. Likewise, U15 and U21 pins 5 are connected.

rasz_pl wrote on 2026-05-19, 20:57:

are pins 6 7 8 linked between U8 U15 U21 U28?

Yep, they are.

rasz_pl wrote on 2026-05-19, 20:57:

Lastly it looks suspiciously like the data bus might be connected between banks making it NOT one 32bit wide pool 😮
Could you please buzz out pins 2 4 15 17 if any are connected between banks?

I tried pair-wise pin 2 from every memory chip to pin2 of every other memory chip, and they are not connected anywhere. Around 12 megaohms between each pair.

Likewise random sampling pin 15 across pairs of memory chips, several megaohms.

Same for pin 17.

Pin 4 are all connected together on each memory chip.

Check out the updated diagram on the URL. Now it is looking a bit more symmetric, so I'm believing it a bit more as well.

Let me know if there's still anything I might have botched up. 😀

To be sure there's no difference in convention.. I understood the pin numbering from this data sheet: https://downloads.reactivemicro.com/Electroni … ata%20Sheet.pdf

Also copied to the diagram.