> cache seems to be statically mapped from 256K-384K physical address

That would make it not really a cache, but just a fast chunk of ram 😀 😮 Implementing Cache controller with only 74 would be a challenge, but PALs should do the trick for simple direct mapping approach.

I would also expect this to only run 486 in non burst mode, so 386 Bus protocol. Burst is kinda complicated for raw 74s and only makes sense if you have good cache controller as it greatly speeds up cache fills.

A20 jumper is weird. A20 was easy to implement, after all it was initially handled by Keyboard controllers with one AND gate 😀 Plus one has to go out of his way to need it - its only required for broken real mode software expecting 1 MB memory wrapping and UMB. Maybe it was meant for 16bit Unix variants like Xenix? Still weird considering 486 L1 cache is A20 aware thur A20M# pin.

The name of the maker, Advanced Integration Research, sounds like they were testing the design of 386dx/486 32-bit cpus in order to make a chipset, but decided to sell a board because the price worked out.

The 16 MHz xtal at the top left of the board throws me off, unless it's a /2 (8 MHz) for the ISA bus.

I am vaguely remembering a 386DX board one of my buddies saved from scrap in the mid 90s. That was 100% logic, full AT size and had jumpers to select between DOS/Xenix/Netware, I do not know what the difference was in operation. I don't think we ever had it running. It also had a HDD controller onboard, but can't recall if it was IDE or SCSI.. maybe even ESDI.

rasz_pl wrote on 2026-05-15, 08:59:

That would make it not really a cache, but just a fast chunk of ram 😀

Yeah, an accidental NUMA. And the 35ns is sufficient since there's no need for the cache to be fast to minimize the miss penalty.