Reply 20 of 30, by rasz_pl
Vlodek_d wrote on 2026-06-24, 09:53:3) xtramtest by David Giller and Adrian Black gives the following result - see photo 3
Unfortunately, I did not find a detailed description of xtramtest, so I still do not understand the reasons for the errors it found.
EM column is for March-U test https://github.com/ki3v/xtramtest/blob/bbf9c3 … marchu.asm#L167
EB is for Bit tests https://github.com/ki3v/xtramtest/blob/bbf9c3 … ganssle.asm#L94
No idea why those labels were chosen, what does the E even stand for? 😀
So your board is failing March-U tests on every second bank while passing bit pattern ones. Normal ram tests will miss this almost every time and claim good ram. SuperSoft is very guilty of this while labeling itself a diagnostic tool.
Now the weird thing is its failing on both base 512KB, which Im guessing is provided by 4x M5M44256 U22 U23 U24 U25, AND also on the extra bit between 576KB and 640KB coming from second bank.
When its failing its on all bits all at once.
Afaik on Sanyo MBC-17Plus (from pictures of pcb on theretroweb) ODD bits are provided by U22 U23 U31 U32. Even bits U24 U25 U33 U34.
Im also guessing all Address lines will be common for all ram chips in a bank, with banks having separate RAS/CAS. Address lines are most likely buffered with U17 U18 and U37 per bank, as those are closest to U20 labeled "MEM CONTL".
This makes it impossible for one bad ram chip to produce such failure. What is much more likely than all 8 bad ram chips is one bad Address line.
You only need first 7 working address lines to address 64KB when using 4x M5M44256 per bank.
I would highly suspect A7 from the computer side, it can be any of the lines on ram chips side) line going to https://datasheet4u.com/pdfhtml/0315/1111256/page-000001.png Ram chips.
Scope would be handy at this point to check if all Address lines are wiggling on ram chip pins during the ram test.
Without scope you can do passive measurements. Continuity test between ram chips A0-A8 and pins of U17 U18 U37. Between U17 U18 U37 and U20. Also between all of those chips and RM09 RM10 RM11 RM12 - those presumably pullups are critical for signal stability.
Best to draw a connection map so you dont get lost. For example mspaint on top of https://theretroweb.com/motherboard/image/1-6 … 46809793866.jpg like here
Re: OG VGA 1987 IBM PERSONAL SYSTEM/2 DISPLAY ADAPTER ram wiring question. https://oummg.com/manual/imgs/IBM_VGA_75X9017XM/closeup/
In theory:
With A7 missing Bit test would run fine because they would be testing same first 64KB of every 128KB region, and since ram is ram they wont notice a difference. Wrote 5, read 5 back, test good.
March test on the other hand should notice we arent really writing to address 1C000 because whatever we write here also magically appears at 0C000, thus is mirrored.
Vlodek_d wrote on 2026-06-24, 09:53:Still, I am not sure that "AT is just a fatter XT with different CPU" - maybe AT (especially with such a strange chipset) should be tested a little differently?
The more modern chipset the higher the chance it will require additional Bios initialization to enable memory controller or unlock an extra bank (example https://github.com/ki3v/xtramtest/issues/12) but in your case it appears ram works out of the box.
https://github.com/raszpl/sigrok-disk FM/MFM/RLL decoder
https://github.com/raszpl/FIC-486-GAC-2-Cache-Module (AT&T Globalyst)
https://github.com/raszpl/386RC-16 ram board
https://github.com/raszpl/Zenith_ZBIOS Zenith Z-386 MFM-300 ZBIOS disassembly