I'm not sure where this is heading now, but sometime ago I did look at the possibility of adding more RAM to the pocket386, so I did look at the addressing of the DRAM, Im no expert on this so I wont be surprised if there is an error in the following, but at least I thought Id offer what I have rather than keep saying its beyond me...
I came to the conclusion that its really not easyto upgrade the RAM on teh pocket 386, prob the best option would be to remove some, or all the DRAM and graft on a 72 pin simm socket. Clearly this isnt trivial! and rather error prone....
The 386sx has a 16bit data bus, so the memory is arranged in 2x Byte wide banks .
How the memory is arranged is one limitation, but also the allowable configurations in the table of the M6117 manual Page 15 puts further limitations on what you can do.
At the moment you have MODE17 as defined in the table, 4 banks of 1M x 2 bytes. 1 DRAM chip is used for each bank.
You cant just double every bank because the table doesnt have an entry for 4 banks of 2M x 2 bytes...
If you want a total of 16MByte, the only option is MODE21, 2 banks of 4Mx2Bytes (- rather surprisingly leaving 2 banks empty....)
(the memory arrangement in the published book 386 schematics doesn't appear to make sense, the CAS/RAS lines dont appear to be connected & its got 256K x 4bit DRAMs??)
my GUESS (we'd need better schematics or to reverse engineer the PCB to be sure) is that on the Book 386 the designer has put 2 banks of 4Mx2Bytes on the main PCB (MODE21) and another two banks of 4Mx2Bytes on the 80387 PCB, MODE30 - but it seems this isnt usable!
on the Pocket 386 the address connections to each DRAM chip from the M6117 are:
1. 12 address lines, MA0 to MA11 (common to all DRAM) are all on the schematic, however I believe in the 2Mx2Byte DRAM chips used MA10 & MA11 (pins 19 &20) are not connected, so only 10 address lines are in use, but the address lines are there to address more memory...
2. Each chip has its own, seperate RAS & two CAS s
The two CAS lines are used to select the high or low byte in each DRAM - they can operate in byte wide or 16bit word modes, depending on the use of these i.e you drive both together for 16 bit wide mode. So at least in theory, the connections are there to allow byte wide access, but I'm not sure if this is used... (IF the chips are in a system that has a byte wide data bus you connect the low and high byte data lines together, they are tristate, enabled by the corresponding CAS line. )
So I think that the M6117 has the required address, RAS & CAS to address 64MByte- but this is the M6117's memory controller interface with the DRAM. The question is how the 386 inside the M6117 is connected to the memory controller to allow it to access this much... I think MA table on page 76 to 78 of the manual may well have a clue here, I get the MA is memory address - the address lines used externally to the DRAM. I guess the A* in the table are the 386s address lines??? But they only seem to go from A1 to A16, the PA entries from PA17 to PA25? Are the A8 and PA* all part of the same address bus??? I dont know!