Thanks! I'll check it out.

Something I should also probably mention...the system hanging at 05h with the Cyrix 5x86 CPU installed on the unpatched BIOS only happens on real hardware. I can't replicate it with PCem.

Okay, I'm back with less than great news.

With the modified BIOS, the system is still locking up at POST code 05h with the Cyrix 5x86 installed. When I NOP out the instruction the skip over the 05h test, now the system locks up at the " Hit <DEL>, if you want to run setup" line. It's also doing this with a standard i80486DX.
Strangely the BIOS works perfectly fine in PCem.

Argh, well that's not good, but as you've said it still works in emulation, so it's hopeless for me to try to repro it without the hardware.

Do you have any 486 boards with a '91 or '92 AMIBIOS?

Anonymous Coward wrote on 2026-08-17, 06:57:

Do you have any 486 boards with a '91 or '92 AMIBIOS?

Not with 3.3V but...

I placed a 5x86-100 and the modified BIOS I uploaded above on an SiS 471 board.
Obviously the chipset is massively mismatched with the BIOS, it detects the wrong amount of memory, but it does (slowly) POST and works well enough for me to boot from a floppy.
It blasts right through code 05 and continues working. No troubles with hanging at Hit <DEL> for Setup.
So,the CPU detection code works on a real 5x86. I also tried an IntelDX4 and it also works.
I checked the Cyrix CCR2 register, the initialization code successfully sets LOCK_NW there.
Next, I put the original unpatched NICE BIOS on.
It also works, and as expected, reports "486DX or 487", and LOCK_NW is not initialized.

The "Cyrix 5x86 hangs on WBINVD if it hasn't been properly initialized yet" theory is officially ruled out as an AI hallucination.
There has to be something deeper here, like the interposer causing your 5x86 to think your chipset supports things that it actually does not support, and it just happens to be tickled by the internal cache flush and external cache flush in post code 05.

I have a DTK PKM-oo31Y, a MCCI/Nice Super EISA, and a Tyan S1437. They all have very similar 91/92 AMIBIOSes, and they all choke on the Cyrix 5x86 in the same way. I have tried 4 different interposers, and attempted modifications on two separate occasions.

Your test with my BIOS on an SiS471 is pretty interesting, and shows that there's more to it than just a BIOS incompatibility. What's odd is that on My DTK PKM-0031Y, Cyrix 5x86 boots normally if I swap out the AMI for MR-BIOS. Based on that test alone, most would conclude that the BIOS is at fault, yet your test implies otherwise.

In any case, bypassing the o5h test works for me and I'm okay with the fact that I may not ever understand why exactly.

The one thing that is invalid with testing on an SiS 471 of course is that it fully implements write-back L1 cache support. So if it's something that only crops up when the chipset doesn't have it, it's not a valid test.

jakethompson1 wrote on 2026-08-17, 07:11:

I placed a 5x86-100 and the modified BIOS I uploaded above on an SiS 471 board. Obviously the chipset is massively mismatched wi […]
Show full quote

I placed a 5x86-100 and the modified BIOS I uploaded above on an SiS 471 board.
Obviously the chipset is massively mismatched with the BIOS, it detects the wrong amount of memory, but it does (slowly) POST and works well enough for me to boot from a floppy.
It blasts right through code 05 and continues working. No troubles with hanging at Hit <DEL> for Setup.
So,the CPU detection code works on a real 5x86. I also tried an IntelDX4 and it also works.

There is MR.BIOS for SIS471 - you can try with this BIOS
https://theretroweb.com/motherboards/s/acer-vi15g

The boards I'm dealing with use the SIS EISA chipset. I doubt too many SiS471 boards came with a hiflex BIOS.
Anyway, it's cool MR-BIOS for SiS471 was finally found.

Hi guys, thanks for inviting me to give my view on this Cx5x86 on old boards/BIOSes issue. I followed this thread with great interest!

I see that a lot of ground has already been covered.
In an earlier 2024-06-02 reply here, I promised to analyze the Asus VL/EISA-486SV1 #401A0-0112 BIOS. I did, but life got in the way and I never followed-up on that. I hope to make good on that soon.
As a first step, here is the complete CPU support list of this BIOS. For CPU detection, only the reset value in DX and the Cyrix DIV test is used. The value in the Cyrix DIR register is not used yet in this early Award BIOS.

Then I have a FIC 4386-VIO socket 1 board (VIA VT495 Venus chipset) to experiment on.
Its 1993 Award v4.50 BIOS has exactly the same CPU support as the Asus 486SV1 BIOS, so no Cx486DX(2) support. I have a Cx486DX-40 and a Cx486DX2-66 to test with. The board is running an i486SX-25 just fine, but in the past I couldn’t get the Cx486DX-40 to POST. I didn’t have a POST analyzer card then, but I do now and expect to find out why the Cyrix doesn’t POST.

I will keep you POSTed! 😀
Jan

Chkcpu wrote on 2026-08-17, 17:12:

Hi guys, thanks for inviting me to give my view on this Cx5x86 on old boards/BIOSes issue. I followed this thread with great interest!

Hello, hopefully we will get to the bottom of this.

I have been DMing Anonymous Coward some more. To summarize, to get it to POST he has NOPed out the dcb9 jmp here:

1seg000:DCB5 B0 05                                      mov     al, 5
2seg000:DCB7 E6 80                                      out     80h, al         ; manufacture's diagnostic checkpoint (POST code)
3seg000:DCB9 E9 D2 AB                                   jmp     sub_F888E

When not NOPed out it ends up here after a few trivial jumpings around:

1seg000:8897 BF 9D 88                                   mov     di, offset loc_F889D
2seg000:889A E9 25 02                                   jmp     loc_F8AC2

and then here:

1seg000:8AC2 0F 01 E0                                   smsw    ax
2seg000:8AC5 A8 01                                      test    al, 1 ; skip if protected mode
3seg000:8AC7 75 14                                      jnz     short loc_F8ADD
4seg000:8AC9 0A E4                                      or      ah, ah ; skip if 386 (or maybe 486SLC/486DLC?)
5seg000:8ACB 75 10                                      jnz     short loc_F8ADD
6seg000:8ACD 0F 20 C0                                   mov     eax, cr0
7seg000:8AD0 66 0D 00 00 00 60                          or      eax, 60000000h ; CD=1 (cache disabled) NW=1 (no write-through)
8seg000:8AD6 0F 22 C0                                   mov     cr0, eax
9seg000:8AD9 0F 09                                      wbinvd
10seg000:8ADB 33 C0                                      xor     ax, ax
11seg000:8ADD
12seg000:8ADD                            loc_F8ADD:                              ; CODE XREF: sub_F8897+230↑j
13seg000:8ADD                                                                    ; sub_F8897+234↑j
14seg000:8ADD FF E7                                      jmp     di

My recommendation to try next is to patch the offset at 8898, to point to dcbc, so that everything in post code 05 after the wbinvd is skipped.
If it still hangs, we've isolated it to this:

1seg000:8ACD 0F 20 C0                                   mov     eax, cr0
2seg000:8AD0 66 0D 00 00 00 60                          or      eax, 60000000h
3seg000:8AD6 0F 22 C0                                   mov     cr0, eax
4seg000:8AD9 0F 09                                      wbinvd

And we can start putting this in .COM files and running it after the system is up and running to see if it still hangs.
If it doesn't hang, it's the external cache flush rather than the internal one that makes it hang.