Since there are still some errors coming in, and it is very hard to work anything out from descriptions and photos alone, this update adds a version marker — the build at the bottom of the page — and writes the settings that generated a file into the file itself. So for any problem, please send me the generated file that is faulty, together with which program and version you used and what error it reports.
Dothan Burger: a non-manifold edge is an edge where the surface does not close up properly — the model has a gap you cannot see, but the slicer trips over it.
About the pedestal: there are two ways of supporting a chip in a pocket. The pedestal is a raised square in the middle of the pocket and the chip rests on its own pin-free centre — that is the "Central pedestal" checkbox. The ledge is a step around the edge of the pocket and the chip rests on the rim of its substrate — that is the "Edge ledge under the substrate rim" slider, in mm, 0 meaning none.
Which one is right depends on the underside of the package. Old CPUs (386, 486, Socket 7, Socket A) have a clean underside, so the pedestal is enough. From Socket 370 onwards they started putting SMD capacitors down there, so those need the ledge — Socket 370 has both, a smaller pedestal plus a ledge, and the newer ones have only the ledge. So for Socket A the pedestal is on and the ledge is 0 by default, and that is deliberate.
Yoghoo: the filament figure is calculated from 100% fill, so the real weight is proportionally lower according to your own settings. A reset for the values has been added, except for the selected package/socket and the label text. The preview can be reset by clicking a view type — including the one that is already selected.
A tray mixing different packages: nope, at least in the near future.
H3nrik V!: the DIP dimensions have been checked and the calculations cleaned up where they had been rounded — and one of them turned out to be a typo rather than rounding, off by half a millimetre. The count was already there, the wording has been changed. And if you like, send me your design and I can look at whether some adjustment could be made so the two fit together.
Separators between chips: not right now, but possibly later this week.
NeoG_: fair enough, and I am not going to pretend otherwise — I do not hand-code all of this myself, the project is AI-assisted. There is simply too much interlinked technology in it for one person to command all of it at that level of detail.
For context: I am an IT analyst/developer/programmer by profession, I studied mechanical engineering at secondary level, and electronics is my hobby. I understand what the project does and I have been checking it from the start — but I am not going to claim that anyone can understand something like this to the last line of code, in all its connections.
As for the posts, they were not plain copy and paste either. Trust but verify: I went through everything, and a good part of it I wrote myself.
