Some old SS7 benchs -

ASUS P5A rev. 1.03, ALi Aladdin V+ rev. E, ext. tag-ram

128MB / GF3 ti200
Win98
AliAGP 1.9
Nvidia 7.76

ALiAGP = Turbo, agp 2x

Stock:

120x5.5

124x5.5

WPC:

DFI K6BV3+/66 rev. B2, VIA MVP3

1MB L3

128MB / GF3
Win98

DX 8.1
VIA 4in1 v4.35 + Viagart.vxd v4.16
7.76_Ti_w9x
vlatency_v019

UDMA/66 tweak:

Stock:

120x5,5:

WPC:

Tekram P5M3-A+

VIA MVP3

1MB L3

128MB / GF3
Win98

DX 8.1
VIA 4in1 v4.35 + Viagart.vxd v4.16
7.76_Ti_w9x
vlatency_v019

Stock:

WPC:

UDMA/66 tweak:

115 x 6

124 x 5.5

133 x 5

120 x 6

MikArt wrote on 2026-10-01, 12:10:

Some old SS7 benchs - […]
Show full quote

Some old SS7 benchs -

ASUS P5A rev. 1.03, ALi Aladdin V+ rev. E, ext. tag-ram

128MB / GF3 ti200
Win98
AliAGP 1.9
Nvidia 7.76

ALiAGP = Turbo, agp 2x

Stock:

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120x5.5

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124x5.5

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Your cpu is a beast

Mamba wrote on 2026-10-03, 14:11:

Your cpu is a beast

I can't send a PM, reply here.

MikArt wrote on 2026-10-04, 11:00:

Mamba wrote on 2026-10-03, 14:11:

Your cpu is a beast

I can't send a PM, reply here.

Spoiler

I replaced the original cache on my P5A 1.03 with LP61L64128F-4:

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The question was, how did you get the cache working at such high FSB frequencies.

Mamba wrote on 2026-10-04, 11:23:

The question was, how did you get the cache working at such high FSB frequencies.

4 ns new cache vs the original 5 ns
It just works.
Of course, it also depends on the revision of the motherboard, the chipset version, VCCio, etc.

GA-5AA, FSB=135, winXP, L3=on:

MikArt wrote on 2026-10-04, 11:50:

4 ns new cache vs the original 5 ns It just works. Of course, it also depends on the revision of the motherboard, the chipset ve […]
Show full quote

Mamba wrote on 2026-10-04, 11:23:

The question was, how did you get the cache working at such high FSB frequencies.

4 ns new cache vs the original 5 ns
It just works.
Of course, it also depends on the revision of the motherboard, the chipset version, VCCio, etc.

GA-5AA, FSB=135, winXP, L3=on:

Spoiler

The attachment 044.png is no longer available

Same external tag ram chip?
I have exactly your P5a revision.
You just changed the chance chip??

Mamba wrote on 2026-10-04, 11:58:

Same external tag ram chip?
I have exactly your P5a revision.
You just changed the chance chip??

Same.
Only cache chip.

What’s the purpose of that wire connected to one of the SRAM pins? It shouldn’t be needed for the cache upgrade…

bloodem wrote on 2026-10-05, 05:59:

What’s the purpose of that wire connected to one of the SRAM pins? It shouldn’t be needed for the cache upgrade…

In the early pcb revisions, this wire is not routed.

A16:

MikArt wrote on 2026-10-04, 12:04:

Mamba wrote on 2026-10-04, 11:58:

Same external tag ram chip?
I have exactly your P5a revision.
You just changed the chance chip??

Same.
Only cache chip.

Can you share the type of chip used in P5a?
I assume it is pin to pin compatible?

Mamba wrote on 2026-10-05, 16:53:

Can you share the type of chip used in P5a?
I assume it is pin to pin compatible?

obvious LP61L64128F-4

I see but this is 1mbyte, I mean just a pin to pin 4ns chip of 512kb.
I do not intend to do the 1mb mod.

Mamba wrote on 2026-10-05, 17:21:

I see but this is 1mbyte, I mean just a pin to pin 4ns chip of 512kb.
I do not intend to do the 1mb mod.

If you simply replace the cache chip with a larger pin compatible version (like the aforementioned LP61L64128F-4), the board will work just fine and treat the chip as a 512kB SRAM (if you don't change the resistor configuration). I know I did this test on one of my P5A-B rev 1.04 boards and it worked fine.
Though, truthfully, you might as well just go all the way and increase the cache to 1 MB, changing the resistors takes a few minutes. 😀