Does anyone know how the Rev G 256-color mode is set? The W32i/p documentation mention it in the ATC 16h register description about the HICOLOR mode. I've currently made the hicolor mode (bit 4 set bit 5 cleared) to drive the upper DAC lines with the high byte and the lower lines with the low byte when PCLK goes high and high byte when PCLK goes low (the ET4000AX documented behaviour, making it comparible with those STG1702 (a known W32i/p board DAC) and SC15025 etc. modes.

Anyone knows something about this "rev G" mode?

Also, what happens on the low 8-bits of AP7:0 when it's in 16-bit mode, during the rising/falling edge of PCLK? It's only documenting AP15:8 in the W32i and W32P documentation. If the ET4000AX documentation is to be believed, the rising edge would have the low byte on AP7:0 and the falling edge the high byte. And AP15:8 would have the high byte during both edges. Thus making it compatible with both 8-bit (not connecting the A15:8 pins) and 16-bit DACs (which can use both rising-only and rising/falling AP7:0 and (rising only) AP15:0 schemes).