Why not use 1024 x 1 DIP20 chips (70 or 80 nS) for a total of 2 or 4MB? These chips ar very common and still widely available plus the socket are there.

majestyk wrote on Today, 08:45:

Why not use 1024 x 1 DIP20 chips (70 or 80 nS) for a total of 2 or 4MB? These chips ar very common and still widely available plus the socket are there.

I have no idea, if 1024x1 chips are compatible with this board. I don't even know the board's make - on TRW site it is listed as "unknown 286 Suntac mobo". There is no official user manual available. The closest memory configurations described are in DFI-RACER-286 rev 0 board manual - for memory banks 2 and 3. The originally installed 128 KB DIP-20 DRAM chips I have are 4-bit. The parity chips are 1-bit, but there are none installed on this board.

But first I want to know what's the maximum access time suitable for 16 MHz with WS 0 set for DRAM.

EDITS: Typos + link to pdf added.

For 4 MB you need 36 DIP 20 chips (1024 x 1), 32 for memory + 4 for parity.
Yesterday I successfully tested 80nS memory chips on a slightly overclocked 16MHz 386SX mainboard at 18 MHz with zero WS.

majestyk wrote on Today, 09:13:

Yesterday I successfully tested 80nS memory chips on a slightly overclocked 16MHz 386SX mainboard at 18 MHz with zero WS.

Thanks! 80 ns seems Ok, but what about 100 ns?

I tested with 8MB and interleaving (4 banks). Without interleaving (1 bank, 2MB) I had to set 1 WS.

8 sockets in 2 banks populated with 8 chips, so my 286 mobo DRAM works in interleave mode, right?

But this is not the question here. My problem is with the access time of 120 ns for the originally installed 256x4 DRAM chips, which turned out to be unsuitable for WS 0 at 16 MHz bus. The new working DRAM wait state setting of 1 completely negates the point of my CPU speed upgrade from 12 to 16 MHz 🙁 I need some faster DRAM chips, but these are also hard to find here, so I will get even 100 ns ones (if price is acceptable), if I'm sure, that they are capable to work with WS 0 at 16 MHz.

It seems I phrased my first question in a not so clear way, so I'll correct it.

Have a look into your BIOS settings if interleaving is enabled or not.

Unfortunately this MR BIOS doesn't show such information, even if it is waaaay more sophisticated than the original Award's c*ap.

I still don't get with what this interleave/non-interleave memory configuration could help in my case, since all the available 8 DIP-20 sockets are populated for a total of 1 MB memory. I don't want to remove chips for interleave configuration, since 1 MB RAM is not enough for this 286 system.

I'd better try playing with increasing the RAM refresh cycle time. I think, I have some programs for this, that work with 8086/88 XT-compatible motherboards, but never tried them on any 286 mobo.

Interleave doesn´t affect the usable memory size, it just provides a faster access strategy like reading from two different blocks simultaneously. Still it slacks off access timings so you get away with "slower" RAM.

Besides that not all chipsets are capable of interleaving. I don´t know if this Suntac does. I found no hint in the datasheets so it might be non-interleave by design.
If it doesn´t or BIOS doesn´t you will have to use faster RAM.

majestyk wrote on 39 minutes ago:

Interleave doesn´t affect the usable memory size, it just provides a faster access strategy like reading from two different blocks simultaneously. Still it slacks off access timings so you get away with "slower" RAM.

Besides that not all chipsets are capable of interleaving. I don´t know if this Suntac does. I found no hint in the datasheets so it might be non-interleave by design.
If it doesn´t or BIOS doesn´t you will have to use faster RAM.

Ok, probably I misunderstood, that you've depopulated some memory banks to change this RAM interleave modes on your 386 mobo. As I noted, I don't have a single clue, if this Suntac ST62C00x (C008) chipset supports such thing and there's nothing about memory interleaving settings in the MR BIOS I use now, nor in the original Award's BIOS thing.

Thanks for your confirmation, that 80 ns DRAM chips will do the job (I was sure about this), but my first question is - are 100 ns DRAM chips "fast enough" to sustain 16 MHz bus with DRAM wait state set to 0, and I still have no answer.