rasz_pl wrote on 2026-11-01, 07:22:

analog_programmer wrote on 2026-11-01, 06:31:

The Panatek PK-009 motherboard, that you're suggesting as a "matching board", looks like mine

Sorry. I assumed unknown-suntac-286 matched your board. Ill admit I didnt look at your picture because its bad quality 😀
imo Panatek PK-009 matches unknown-suntac-286. I resized and distorted images to match size and was flipping between them, the only difference I could spot was guard copper pours around mounting holes.

I just don't want another useless "[Unknown] (Suntac 286)" article with my board's pictures to pop-up on TRW site, so I didn't care to provide any hi-res quality pictures in the Predator99's thread. And the DIP-switches + jumpers "manual" I managed to compose is mainly for my own usage, since still no one has come out with exactly the same board, nor anyone shown any interest about it.

As for the Panatek PK-009 and the "[Unknown] (Suntac 286)" board from TRW site - if not a perfect match in their circuits, they look very similar to me, but there's no info about any jumper/DIP-switch settings on the unknown board, so we can only speculate for "a match".

rasz_pl wrote on 2026-11-01, 07:22:

analog_programmer wrote on 2026-11-01, 06:31:

, but only visually - there are some minor differences in the circuit and the components located "above" the crystal oscillator.

yours does indeed look different, that circuit might be 0 wairstates implementation, looks similar to whats in panatek manual.

Indeed. Close match, but not full match. And the most important difference - the mismatch in the DSP1 DIP-switches functions. That's why I din't pointed to Panatek PK-009.

And back to main topic. Last night I watched a YT-video from some "beaver" and he used some fast SOJ FPM RAM chips with his own ugly DIP-20 PCB adapters for VRAM upgrade (just faster chips, not more VRAM). So, it seems like I will have to look for SOJ DRAM chips with faster access times (possibly lower than 65 ns) and bigger volume + some suitable SOJ-26 to DIP-20 PCB adapters (I like these, but pcbYay became pcbNAY so far, so it's not an option to me for using these chinese PCBs making services anymore).

Or I have to look for slow SRAM DIP-20 (cache) chips, if there are any 512x4/1Mx4. I already know how to stop PIT Channel 1 refresh cycles and so the DRAM refresh cycles for these ancient PC systems, even if there's no such option in the BIOS. Nope, rasz_pl explained in details, that SRAM chips can not be a direct replacement for DRAM chips.

EDIT: DRAM-to-SRAM replacement needs some serious hardware modifications.

analog_programmer wrote on 2026-11-01, 08:00:

I just don't want another useless "[Unknown] (Suntac 286)" article with my board's pictures to pop-up on TRW site, so I didn't care to provide any hi-res quality pictures in the Predator99's thread.

but you didnt provide those here either 😀 you are the only person able to spot those differences

analog_programmer wrote on 2026-11-01, 08:00:

Indeed. Close match, but not full match. And the most important difference - the mismatch in the DSP1 DIP-switches functions. That's why I din't pointed to Panatek PK-009.

you linked to unknown-suntac-286 and imo its 100% same board as panatek-pk-009 😁 thus whatever matched in one matches in the other

analog_programmer wrote on 2026-11-01, 08:00:

Or I have to look for slow SRAM DIP-20 (cache) chips

umm sram chips need separate address bus, would requiring additional circuit bypassing chipset mem controller, latching address from cpu etc

solder two 30pin simm sockets, or just solder short wires to simms directly and plug into sockets, will probably work fine at 16MHz

rasz_pl wrote on 2026-11-01, 11:54:

analog_programmer wrote on 2026-11-01, 08:00:

I just don't want another useless "[Unknown] (Suntac 286)" article with my board's pictures to pop-up on TRW site, so I didn't care to provide any hi-res quality pictures in the Predator99's thread.

but you didnt provide those here either 😀 you are the only person able to spot those differences

I didn't published new picture here either, because I'm not proud of my DIY SMD-to-"full-can"-crystal-oscillator adapter. I had to do such thing, because I didn't manage to get trough-hole mount (DIP?) crystal of 32.000 MHz, but got much smaller one for surface mount.

rasz_pl wrote on 2026-11-01, 11:54:

umm sram chips need separate address bus, would requiring additional circuit bypassing chipset mem controller, latching address from cpu etc

solder two 30pin simm sockets, or just solder short wires to simms directly and plug into sockets, will probably work fine at 16MHz

Interesting. I read somewhere on the i-net, that back in the times some people installed SRAM chips instead of DRAM for maximum performance on (8088/86 and V20/30) XT-motherboards without any modifications (except the software setting for PIT ch.1 refresh stop). I'll have to search for this info again.

But where exactly I have to solder those 30-pin SIMM sockets, since there are no trough-holes left for such things? 😁 This board is full of DIP sockets for DRAM chips - in general same layout as the Panatek PK-009 and the TRW-unknown one.

analog_programmer wrote on 2026-11-01, 12:13:

I read somewhere on the i-net, that back in the times some people installed SRAM chips instead of DRAM for maximum performance on (8088/86 and V20/30) XT-motherboards without any modifications

imposibru, sram requires separate stable latched address bus and cs
Either extra circuit for latching RAS part of address like here in c64 sram-dram repleacement https://github.com/hkzlab/C64_250407_SRAM_Ada … ram_adapter.pdf

or entirely bypassing ST62BC002 by decoding 286 bus signals directly https://www.youtube.com/watch?v=PRslR3aA57Q + own address decoder to not map over ROMs and IO cards
all in all $20-50 in SRAM chips + hours designing and debugging decode logic to arrive on something solvable with two SIMMs soldered directly to the board

analog_programmer wrote on 2026-11-01, 12:13:

But where exactly I have to solder those 30-pin SIMM sockets, since there are no trough-holes left for such things?

as you indeed noticed "this board is full of DIP sockets for DRAM chips" board is already full of pre-made holes 😉
variants with SIPP/SIMM sockets wire those sockets to DIPs https://theretroweb.com/motherboards/s/unknown-js-168a
just a matter of mapping out, soldering wires to simms and sticking those wires to correct DIP socket holes
https://www.alexandrugroza.ro/microelectronic … 3A%20Electrical

analog_programmer wrote on 2026-10-31, 09:15:

majestyk wrote on 2026-10-31, 09:13:

Yesterday I successfully tested 80nS memory chips on a slightly overclocked 16MHz 386SX mainboard at 18 MHz with zero WS.

Thanks! 80 ns seems Ok, but what about 100 ns?

Its almost universal that memory chips need to be figured as being 1:1 rated for zero wait states on old systems like a 286

100ns ram = 10mhz so in nearly all cases is only usable at 10mhz with 0 wait unless the ram works overclocked (the math is simple so I won't go over why this is)

Lots of folks will talk about hit miss bus cycles and other nonsense about why slower async ram might work faster but the reality is that nearly all boards eat up the other half with latency making this aspect irrelevant.

Your board using 120ns ram for 12mhz means one of 2 things that chipset latency is very low as that normally is out of spec or that somebody tested and pushed the edge of commodity chips.

Without manual listing the ram required for each clock speed we are only guessing.

On spec (what normal systems typically require for 0ws)
10mhz = 100ns
15mhz = 75ns
20mhz = 53ns (don't ask real systems used that)
25mhz = 40ns

I had a Harris 25mhz system with 60ns ram running 0ws, came that way from the factory and the ram ran hot, eventually dying.

rasz_pl wrote on 2026-11-01, 22:41:

imposibru, sram requires separate stable latched address bus and cs Either extra circuit for latching RAS part of address like h […]
Show full quote

imposibru, sram requires separate stable latched address bus and cs
Either extra circuit for latching RAS part of address like here in c64 sram-dram repleacement https://github.com/hkzlab/C64_250407_SRAM_Ada … ram_adapter.pdf

or entirely bypassing ST62BC002 by decoding 286 bus signals directly https://www.youtube.com/watch?v=PRslR3aA57Q + own address decoder to not map over ROMs and IO cards
all in all $20-50 in SRAM chips + hours designing and debugging decode logic to arrive on something solvable with two SIMMs soldered directly to the board

You're right. Now I see in details why SRAM chips are not direct replacement for DRAM chips, despite the statements, which I read some time ago in a local "scrap" (I mean "old") electronics repair forum. Such DRAM-to-SRAM modification is doable, but too complicated, and I think at the end it will not worth the efforts, the time and the € invested.

I should not trust to such common statements form a random people thrown at some i-net platforms without any details or evidences provided. My idea for using some SRAM chips instead of DRAM ones now goes to thrash bin and I'll stick to SOJ-to-DIP DRAM adapters modification.

rasz_pl wrote on 2026-11-01, 22:41:

as you indeed noticed "this board is full of DIP sockets for DRAM chips" board is already full of pre-made holes ;) variants wit […]
Show full quote

as you indeed noticed "this board is full of DIP sockets for DRAM chips" board is already full of pre-made holes 😉
variants with SIPP/SIMM sockets wire those sockets to DIPs https://theretroweb.com/motherboards/s/unknown-js-168a
just a matter of mapping out, soldering wires to simms and sticking those wires to correct DIP socket holes
https://www.alexandrugroza.ro/microelectronic … 3A%20Electrical

Thanks for the suggestion, but this seems much more complicated solution, than just using some DIY SOJ-to-DIP DRAM adapters. And I'll end up with some hanging spaghetti-like-wired memory 😁

rmay635703 wrote on 2026-11-02, 00:14:

Its almost universal that memory chips need to be figured as being 1:1 rated for zero wait states on old systems like a 286 […]
Show full quote

Its almost universal that memory chips need to be figured as being 1:1 rated for zero wait states on old systems like a 286

100ns ram = 10mhz so in nearly all cases is only usable at 10mhz with 0 wait unless the ram works overclocked (the math is simple so I won't go over why this is)

Lots of folks will talk about hit miss bus cycles and other nonsense about why slower async ram might work faster but the reality is that nearly all boards eat up the other half with latency making this aspect irrelevant.

Your board using 120ns ram for 12mhz means one of 2 things that chipset latency is very low as that normally is out of spec or that somebody tested and pushed the edge of commodity chips.

Without manual listing the ram required for each clock speed we are only guessing.

On spec (what normal systems typically require for 0ws)
10mhz = 100ns
15mhz = 75ns
20mhz = 53ns (don't ask real systems used that)
25mhz = 40ns

I had a Harris 25mhz system with 60ns ram running 0ws, came that way from the factory and the ram ran hot, eventually dying.

Thanks for the information!

So, these V53C104P12L 120 ns chips are already overclocked and pushed over their limits at the original frequency of 12 MHz with WS set to 0, but somehow they manage to work.

According to bus frequency - access time dependencies you gave, I have to swap them with some faster 70 ns (or even 60 ns) DRAM chips.

I can sacrifice four so-so quality 1 MB 30-pin SIMM FPM RAM sticks with 1Mx4 70ns DRAM chips for the experiment to see if 4 MB of memory could be installed into the motherboard's eight DIP-20 sockets. And of course I'll need eight SOJ26-to-DIP20 adapters (also four SOJ26-to-DIP18 adapters, is I use the parity chips).

"4 MB ought to be enough for a brain-dead 286 😁 " - Gilliam W. Hates IV

Your system may not be overclocking ram as we need a datasheet to know it's actual ram decode latency.

But 70ns is likely ideal many 16mhz systems would work with 80ns, it all depends on the latency of the motherboard memory controller and chipset.

Your hit miss cycle at 16mhz is 120ns

If you use 80ns ram this leaves 40ns for your motherboard components to decode

The fact that your motherboard can use 120ns ram at 12.5mhz means that a hit miss cycle of 160ns - 40ns motherboard/chipset latency= 120ns

A 40ns response time for motherboard decoding is very good for an older 286 (old AT ERA systems could take up to 100ns of decode)

Very modern (1992+) and very rare 286 systems sometimes had very low decode latency ~10ns