64bit has more general purpose registers.
It is practically always faster than 32.
SSE is a 128bit wide integer unit which can run 16x8bit integer operations simultaneously.
https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions
Assuming you're working on pairs of RGBA, that means 8 operations, or 2 pixels simultaneously in theory.
Eg, R1+R2, G1+G2, B1+B2, A1+A2, R3+R4, G3+G4, B3+B4, A3+A4
It would depend on the operation, of course, but for a simple addition that is basically how it works.
AVX is similar, but floating point.
It's "wasteful" to work on effectively 8 bit numbers, but with eight 32-bit single-precision floating-point numbers, you effectively repeat the above.
Eg, R1+R2, G1+G2, B1+B2, A1+A2, R3+R4, G3+G4, B3+B4, A3+A4
So if you use both units, you could have a 2 stage "pipeline" in whatever order makes the most sense given converting int > float is implied.
Possibly the FBI is one and TMU the other?
We're talking 2+ghz cpus capable of 16 simultaneous operations trying to emulate a tiny little 50mhz ASIC here. I can't imagine it's not possible to do the equivalent of an SLI voodoo2 comfortably on one core IF the memory can be fetched/cached properly, and both SSE and AVX are pumping.
There has to be a way to break the workload into chunks that suit a CPU's cache/memory architecture.
By function? TMI/FBU =AVX/SSE?
By colour? R first, G, B, then alpha?