Has anyone seen this POD information? \ VOGONS

Has anyone seen this POD information?

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First post, by sliderider

Posted on 2011-05-04, 10:59

sliderider Offline

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http://www.intel.com/support/processors/overd … b/cs-012627.htm

What does it mean "incorrectly supports write-back mode"? Does it mean the systems support it when they shouldn't or they support it but execute it incorrectly so errors are generated? Does this interposer socket disable write-back completely and enable write through or does it prevent any errors generated by the motherboards that don't support it correctly?

Reply 1 of 1, by Tetrium

Posted on 2011-05-04, 11:05

Tetrium Offline

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My guess is it switches the WB cache on the POD to WT. I'd be interested in learning what exactly the interposer does 😉

Edit:Found this, the pinout to Socket 3.
Might provide an answer.
Link: http://ptgmedia.pearsoncmg.com/images/chap3_0 … nks/03fig15.gif

On a forum I've read that all this interposer does is disable one single pin 😉

Edit2:More info here http://mysite.verizon.net/pchardwarelinks/486pin.htm
It also has a link directly to Intel

Edit3:Direct link to the intel document, it provides a LOT of details including it's WT and WB data.
Link: http://www.intel.com/design/pentium/datashts/29054401.pdf

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