p54c 1.5x (not 3.5x)
p55c usually 3.5x, but some early ones may do 1.5x
k5 dunno
k6 3.5x
k6-2 old 3.5x and 2x
k6-2 cxt/k6-2+/k6-3/k6-3+ (i know this surely reads 3.5x and 6x, no 1.5x or 2x) this is correct 😉
cyrix 6x86/6x86mx/m2 dunno
idt c6/winchip dunno
rise mp6 dunno

At least some K6-3 revisions support 2x multipliers, hence the ability to use one in this comparison:
133 MHz Challenge - 5th/6th gen CPU per clock performance

The K5s all used the same jumper settings as P54 chips of the same P-Rating (not clock speed). Thus, an early model K5 P90 or P100 (at true 90 or 100 MHz) would use 1.5x, while the later model P120, 133, 150, 166, or (unreleased) 200 parts would use the same 2x, 2.5, or 3x jumper settings as P54 counterparts but would internally recognize a different multiplier for the actual clock speed. (PR120 runs at 1.5x60=90, PR133 is 1.5x66=100, PR150 is 1.75x60=105, PR166 is 1.75x66=116.7, PR200 is 2x66=133)

Cyrix 6x86 classic chips also use different multipliers altogether, neither corresponding to PR or clock equivalents consistently and only using integer multipliers of 1x, 2x, or 3x. I need to double check what Intel multiplier settings correspond to Cyrix chips.

For the 6x86MX/MII chips, I believe similar multiplier settings to the P55C and K6/K62 (early models) are used with 2x, 2.5x, 3x, 3.5x, and 4x (and I think 4.5, 5.5) being supported. Albeit, 4x was the highest multiplier any commercially produced MII actually used at stock settings in the 266 MHz PR333. (the very rare PR433 would also be within spec at 4x75 MHz, though the default set-up is 3x100)

kool kitty89 wrote:

At least some K6-3 revisions support 2x multipliers, hence the ability to use one in this comparison:
133 MHz Challenge - 5th/6th gen CPU per clock performance

he said k6-3 multiplier is software adjustable, thats how he did it. without software adjusting it would just boot at 6x.

I think it has to do more with the motherboard than anything else. I'm willing to bet that the bios looks at what cpu is present before it reads the multiplier settings.

luckybob wrote:

I think it has to do more with the motherboard than anything else. I'm willing to bet that the bios looks at what cpu is present before it reads the multiplier settings.

i can't afford to bet, but your idea doesn't seem to explain why most pentium3/4 boards still have (useless) multiplier settings, which only work with unlocked engineer samples. 😉

so heres how my theory works:
1. at booting, board sends a signal to cpu through certain pins: "you should run at 3x fsb" (or other values, set either by jumper or in bios).
2. cpu reads the signal and set its multiplier(if its not locked), deciding its clock.
3. if cpu multiplier is locked, then it simply ignores the signal and insist on its internally fixed ratio.

noshutdown wrote:

so heres how my theory works:
1. at booting, board sends a signal to cpu through certain pins: "you should run at 3x fsb" (or other values, set either by jumper or in bios).
2. cpu reads the signal and set its multiplier(if its not locked), deciding its clock.

Different CPU models/types can also interpret the same signal differently rather than sticking with a fixed standard for multiplier values. As with 6x86 (classic), K5 (PR120/133/150/166/200), and also with 1.5x (P54) being re-used as 3.5x in P55, K6, and 6x86MX/MII, plus 2x repurposed as 6x in late model K6-2s.

Motherboard manuals written after the introduction of such CPUs usually list those alternate multiplier mappings too.

3. if cpu multiplier is locked, then it simply ignores the signal and insist on its internally fixed ratio.

I'm not sure this is always the case, some locked CPUs may simply fail to boot if set at an incorrect multiplier. Specifically, this may be the case for early locked examples that only prevented higher multipliers from being used (as with the Pentium MMX and early Pentium IIs).

no, the motherboard is what determines everything. One of the first things the bios does during post is to probe the cpu. the second is to probe its jumper settings and/or bios setting in ram. The cpu is DUMB. What intel did with locked multipliers is use a laser to cut certain parts of the chip. In doing so intel essentially set the multiplier setting for you. The chipset will read this and will FORCE the multiplier setting, effectively ignoring any user input. if the bios probe cannot determine the multiplier from reading the data off the cpu then it turns to the onboard jumper settings. Athlons were FAMOUS for having the bridges availible to the end user. Ever use a gold finger on a slot A? The pencil mod on an athlon xp?

Its simple logic. if processor cannot be read, use motherboard settings. Thats why engineering sample are "unlocked" Intel diddnt cut the wires inside the cpu that tell the chipset what multiplier to use. I can go into step-by-step detail if I need to, but thats how it works.

luckybob wrote:

no, the motherboard is what determines everything. One of the first things the bios does during post is to probe the cpu. the second is to probe its jumper settings and/or bios setting in ram. The cpu is DUMB. What intel did with locked multipliers is use a laser to cut certain parts of the chip. In doing so intel essentially set the multiplier setting for you. The chipset will read this and will FORCE the multiplier setting, effectively ignoring any user input. if the bios probe cannot determine the multiplier from reading the data off the cpu then it turns to the onboard jumper settings. Athlons were FAMOUS for having the bridges availible to the end user. Ever use a gold finger on a slot A? The pencil mod on an athlon xp?

Its simple logic. if processor cannot be read, use motherboard settings. Thats why engineering sample are "unlocked" Intel diddnt cut the wires inside the cpu that tell the chipset what multiplier to use. I can go into step-by-step detail if I need to, but thats how it works.

The CPU handles the actual multiplication though . . . the FSB clock is the only clock signal the CPU actually receives (it multiplies it internally), so the motherboard is simply sending the necessary signal to set the chip's internal multiplier. Hence, locked chips have the internal multiplier unable to be set externally, or unable to be selected beyond a certain point. (as with early Intel locked chips like the P55C and early PII)

There's also the separate issue of BIOS controlled CPU set-ups and old-fashion jumper based settings where the user can only adjust the multiplier/FSB/voltage/etc via jumpers (or switches) rather than being able to select things through the BIOS. (of course, BIOS based set-up has become standard now, though it's not as foolproof in some respects)

We're mainly talking about old CPUs and old motherboards here, where purely jumper selected set-ups (and totally unlocked CPUs) were common.

Additionally, if it was solely up to the motherboard to select the multiplier setting (for locked CPUs), then wouldn't older boards/chipsets predating locked chips be unable to detect CPUs with locked settings? (like running a P55C in a 430FX board)

And on another note, I checked the old 6x86 settings and:
Intel P54 1.5x maps to 3x for Cyrix
P54 2x maps to 2x
P54 2.5x maps to 1x

The 6x86MX/MII maps similarly to P55C and K6/K6-2. (without the 6x multiplier)

kool kitty89 wrote:

The CPU handles the actual multiplication though . . . the FSB clock is the only clock signal the CPU actually receives (it multiplies it internally), so the motherboard is simply sending the necessary signal to set the chip's internal multiplier. Hence, locked chips have the internal multiplier unable to be set externally, or unable to be selected beyond a certain point. (as with early Intel locked chips like the P55C and early PII)

thanks for the info, can you dig up how idt c6 and rise mp6 interpret clock ratios aswell?

noshutdown wrote:

so heres how my theory works: 1. at booting, board sends a signal to cpu through certain pins: "you should run at 3x fsb" (or ot […]
Show full quote

so heres how my theory works:
1. at booting, board sends a signal to cpu through certain pins: "you should run at 3x fsb" (or other values, set either by jumper or in bios).
2. cpu reads the signal and set its multiplier(if its not locked), deciding its clock.
3. if cpu multiplier is locked, then it simply ignores the signal and insist on its internally fixed ratio.

This is how it works with slot-1 and socket-370 boards. The pins are used for sending the multiplier info at POST, then after a few seconds the pins are used for another purpose. That is why changing multiplier jumpers after boot has no effect. The signal is just a binary code, it depends on the CPU what is done with the code.

Source: Intel datasheet I read a while ago.

As far as I am aware, the BIOS attempts to write/set the multiplier registers of the CPU. The BIOS is given information by the BIOS programmer about the location of the CPU's multiplier registers. The CPU can choose to ignore attempts to write to the multiplier registers, that is, if it is locked. Most Cyrix 5x86 chips, for example, ignore the 4X multiplier request. The request to ignore by be burned into the logic of CPU, or LASER modified, as someone mentioned. Depending on the age of the motherboard, the BIOS interprets the user's jumper settings as 'on' or 'off' as direct digital 1-bit inputs, perhaps through pull-up or pull-down resistors. For more modern motherboards, the BIOS auto-detects CPU multipliers, perhaps either by a pre-programmed set of expectations based on CPU type, or by attempting to write to multiplier registers at boot to see which are writable. The multiplier is then set in the CMOS by the user based on the writable options. The manual of each CPU contains information of which registers control frequency multiplication. All CPU frequency multiplication is done by a phase-lock loop multiplier built into the CPU layout pattern.

I'm not sure where you are going with this question.

how do each kind of cpu recognize 1.5x/3.5x and 2x/6x signals?

But to answer as directly as possible, the BIOS writes 1's or 0's to a CPU's register blocks and the CPU looks at which register has a 1 and which has a 0, and from a pre-programmed logic table, sets the P and M values of the PLL accordingly. Most PLL's these days have at least 100 decimal-precision multiplier frequency options which are user adjustable. For more detail, reference PLL in google search.

Of course the BIOS can do the multiplier jumpers for you, on some motherboards. Some have both methods. But the principle is the same.

Anyways, Someone needs to quote the relevant section of the socket 7 specification.

EDIT:
Regarding Socket 5/7 Pin BF0 and BF1, from the Intel Pentium 75 to 200MHz Specification, Order Number 241997-010, june 1997:

BF[1:0] : Bus Frequency determines the bus-to-core frequency ratio. BF[1:0] are sampled at RESET, and cannot be changed until an […]
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BF[1:0] : Bus Frequency determines the bus-to-core frequency ratio. BF[1:0] are sampled at RESET, and cannot be changed until another non-warm (1 ms) assertion of RESET. Additionally, BF[1:0] must not change values while RESET is active.
.....
Core Frequency (max) ; External Bus Frequency (max) ; Bus/Core Ratio ; BF1 ; BF0
200 MHz ; 66 MHz ; 1/3 ; 0 ; 1
166 MHz ; 66 MHz ; 2/5 ; 0 ; 0
150 MHz ; 60 MHz ; 2/5 ; 0 ; 0
133 MHz ; 66 MHz ; 1/2 ; 1 ; 0
120 MHz ; 60 MHz ; 1/2 ; 1 ; 0
100 MHz ; 66 MHz ; 2/3 ; 1 ; 1
100 MHz ; 50 MHz ; 1/2 ; 1 ; 0
90 MHz ; 60 MHz ; 2/3 ; 1 ; 1
75 MHz ; 50 MHz ; 2/3 ; 1 ; 1

- Other/Later CPUs take the same BF1+BF0 signals, but may map them to different ratios. There are only 4 different choices to communicate here. Example: The MMX processor interprets the original 1.5x setting to be 3.5x.
- Intel Started locking the Ratio inside their consumer CPUs around 1998.
- The same goes for the Pentium II/III and their Celeron versions on Socket 370 and Slot-1. Intel specified 4 pins for the multiplier settings with these (=max 16 choices).
- The BIOS does not add much or anything to this matter. In a jumperfree mainboard the BIOS often limits the choices and mislabels them for certain CPUs.

Regarding Super Socket 7 (Source):

AMD added a third jumper for super socket 7, adding more possible codes, for […]
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AMD added a third jumper for super socket 7, adding more possible codes, for

BF2 BF1 BF0 multiplier
1 0 0 3.5x
1 0 1 2.0x
1 1 0 2.5x
1 1 1 3.0x

0 0 0 4.5x
0 0 1 5.0x
0 1 0 4.0x
0 1 1 5.5x

Later K6-2 processors changed 2.0x to be 6.0x (so 400MHz could be reached with a 66 MHz FSB)

The AMD K6-2+ and K6-III+ have an additional way to set the multiplier by software, details unknown.