gerwin, yes I was refering to you. Don't know how the Vetz got in there - I was probably viewing multiple threads.
3x was deliberatly not listed in my post.
A 4x-capable Cyrix 5x86 chip, when booted in 4x mode, can only switch between 1x, 2x, and 4x, not 3x.
A 4x- or 3x-capable Cyrix 5x86 chip when booted in 3x mode, can only switch between 3x and 1x.
A 3x-capable Cyrix 5x86 chip when booted in 2x mode, can only switch between 2x and 1x.
gerwin wrote:Since the hardware is not communicating the proper value, mine and other people's software won't display the proper value.
Is the improper value repeatable and unique for 1x, 2x, 3x, and 4x? If so, can use these static improper values as a calibration means to display the proper multiplier values?
gerwin wrote:I Suppose you could check half clock mode with a benchmark. Though I don't know what you mean with it going out of half clock mode. Anyway, it did not do anything for me. Half clock speed seems to be a myth, just like multiplier readout.
When HLF_CLK is set, the internal CPU frequency will run at half the FSB, but only when the bus is idle. When a bus transfer occurs, the CPU frequency shoots up to the frequency from the time before you set HLF_CLK. When the bus transfer has completed, the CPU frequency will go back to half the bus frequency. When running a benchmark, an external bus tranfer takes place because the benchmark is being loaded from the HDD. During the benchmark, data will continue to be read from either HDD, L2 cache, or memory such that the internal CPU speed stays high. If a very small benchmark app. is run which resides entirely in L1 cache, perhaps the internal CPU frequency stay at HLF_CLK? Did you remove the ability to set HLF_CLK from your SETMUL program? Can you reimplement it? Using the Evergreen utility to set HLF_CLK requires more brain power!
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