16-bit ISA bus have 11 interrupt lines for each slot. B4 (IRQ2), B21-B25 (IRQ7-IRQ3) and D3-D7 (IRQ10-IRQ12, IRQ15, IRQ14) pins. Each ISA card can grab one of them. And each IRQ line can support 1 device only.
Standard PCI bus have only 4 interrupt lines in each slot. Int#A-Int#D, A6, B7, A7 and B8 pins. But each can be used by several devices = shared. Shared devices can't use IRQ in the same time.

To get a full range of PCI Int A-D IRQ's, you must have 4 free ISA IRQs, otherwise the PCI ones share even more, so disable the COM ports in BIOS if not using them.

PCI uses level based, rather than edge based IRQ like ISA, so devices can share, but certain devices will not (SCSI cards generally want a unique one).
Where things have to share, it's best to keep the busiest ones separated.

Also, the IDE/ATA normally occupies INT 14/15 whether it's ISA or PCI, so slots 2 and 3 may be clear, but can be shared if short of IRQs

Think of (I)nter(R)upt re(Q)uests as electrical lines that the devices can use to signal to the CPU that they need its attention. If you have 6 devices that sometimes needs to interrupt the CPU because they have something important to tell it, then it is nice if also have 6 IRQ lines. Then it is simply a matter of each device signalling on its assigned IRQ-line and the CPU will immediately know who signaled and what to do. Simple, fast, etc.

But what do you do if you only have 6 lines and 10 devices? Then some of them must share an IRQ-line. And the CPU will have to ask each of the devices "Was it you?" when the line is pulled. That is a bit slower, and it requires the devices to smart enough to answer the CPU when it comes asking.

The added issue with IRQ was that in the days of pure ISA / VLB, interrupts were edge driven, so could not share - if a second interrupt occurred before being cleared, it would be lost.

PCI interrupts are level driven, so when shared, after the first is cleared, the second is still signalling for attention, so PCI can and does share, but some devices and drivers are not good with it.

For optimal performance, it's best if simultaneously active devices do not share, but with many systems not bothering to give a table, it's not worth being too fussy unless something fails to work.

Under old style "PIC" (programmable interrupt controller), there are no extra IRQs, so the PCI ones are stolen from the ISA pool (hence, make sure there are 4 unused).
Under the newer "APIC" (advanced...), there are additional PCI IRQs.

Finally, every PCI Slot has access to INT A-D for devices that may (a few combined devices) use more than 1 - the allocation is rotated between slots, as all devices use their own INT A line.

PS. From BIOS Optimization Guide, it says most VGA cards do require an IRQ, so the option should be enabled.

Why is this in the DOS games forum? Perhaps Milliways or Marvin?

Moved to Marvin.

In the Phase 22 manual, there is a detailed explanation with exemples of PIC and APIC on two different mobos.
See PDF page 39 : http://www.terratec.ultron.info/Producer/PHAS … 2_Manual_GB.pdf