Interleaving is a chipset-feature.
The idea is to get more performance out of slow memory by using multiple banks in parallel.
For example, if you have 4-way interleaving, the 1st byte comes from the first bank, the 2nd byte comes from the second bank etc.
The reason why you would interleave is because the speed is higher in all cases. If you didn't interleave the memory, but just put the banks next to eachother linearly, then you can only get higher speed when you access from different areas of memory, where most memory accesses in software are usually linear, or at least in the same region.

So yes, it is desirable, and if possible, you should enable it.
In systems with two or more channels of memory, you have to make sure that you install the DIMM sticks in the proper slots. Some chipsets will not work at all if you don't pair the DIMMs properly. Other chipsets will work, but with reduced performance because they cannot perform the interleaving.

Allright. That is the part I understood. Now: how I can know if a motherboard has this feature? Does it shows in bios features? Or it could be automatically enabled by putting the sticks in the right way?

Thank you scali!

ramiro77 wrote:

Allright. That is the part I understood. Now: how I can know if a motherboard has this feature? Does it shows in bios features? Or it could be automatically enabled by putting the sticks in the right way?

I'd say these depend on the hardware itself. Some boards may do it automatically and some may have to be set to interleave, I think this can even differ between boards even if they use the same chipset (provided the chipset supports that). Best is to read the manual. Some boards of a certain era may have had memory interleaving as it was important (I think the higher end 486 PCI boards are a good example of this edit:see Feipoa's reply below this one, some 486 boards do cache interleaving, not memory interleaving , another being some of the newer DDR3 boards though I figure it's technically a bit different, feel free to correct me if I'm wrong).

But anyway, I think it's actually a good idea to to through the BIOS of a board you intent to use and check it's features. These features may even differ between BIOS file revisions of the same motherboard. Another way to find out is by reading other sources of info, like old reviews (these are often filled with buzzwords but also often actually test how this new hypersuper feature performs. They are however very old of course), forum threads (including sites like Vogons or overclocker sites for instance), old manuals, reading about the chipset of the board (like wiki pages about a certain chipset) can also be a good source of info.

But fastest is to check the actual BIOS and just run down all the menus 😀

I do not beleive SiS 496 or UMC 8881 PCI-based chipsets use DRAM interleaving; they use cache interleaving though. Some 386 chipsets use DRAM interleaving, but I forget exactly which. I want to say VLSI Topcat and maybe the SiS Rabbit, but I do not feel like digging through the datasheets.

feipoa wrote:

I do not beleive SiS 496 or UMC 8881 PCI-based chipsets use DRAM interleaving; they use cache interleaving though. Some 386 chipsets use DRAM interleaving, but I forget exactly which. I want to say VLSI Topcat and maybe the SiS Rabbit, but I do not feel like digging through the datasheets.

Ehh whoops, I mixed up memory and cache interleaving! 😵
I think it was more some graphics cards that had memory interleaving like some of the Virges and perhaps some ISA/VLB graphics cards 😊
Anyway, you are correct! 😁

Jajaja yes, I was talking about sdram interleaving. The manual of my Soyo is very weak about its features. It only mentions the chipset (440bx). And there isn't any option in bios.

The 440BX chipset does not support memory interleaving. It's a straightforward PC100 SDRAM to 100 MHz FSB system.

Ok, that's bad. But good to know it! Thank you Scali! 😀

I remember interleaving on 386 and 386sx systems, then it faded away.

The VIA chipsets had something that is called "interleave", but isn't - unlike 386 era interleave, which directed access to alternate banks, the VIA "interleave" allows a page to be held open in each bank.

The modern version is dual channel memory.

Probably the most typical example of interleaving in the P3 era would be the VIA 694X (Apollo Pro 133A) chipset.
This has a typical 64-bit (72-bit with ECC) memory bus. It supports interleaving, but it can't actually have more than 64-bits of data on the bus at one time.

On this chipset, interleaving can only serve to reduce the time wasted on latency. It can get something useful done on one module while waiting for the other. I don't know what the precise behavior is, so I'll just quote Matth79:

Matth79 wrote:

The VIA chipsets had something that is called "interleave", but isn't - unlike 386 era interleave, which directed access to alternate banks, the VIA "interleave" allows a page to be held open in each bank.

The end result should be that even though the bus width isn't any larger, less time is wasted during latency so the memory bus achieves higher utilization.

The 694X datasheet is here, but I didn't see much in it about interleaving:
http://www.datasheetarchive.com/VT82C694X-datasheet.html

The datasheet mentions it can handle either 2-way or 4-way interleaving depending on the size of the RAM chips. I wonder if it has any problem with interleaving two sides of a single memory module that has two 64-bit rows of RAM present.

From what I've seen in memtest86, it appears to me that interleaving on this chipset only makes a small improvement in sustained transfer rate. I don't know if it helps more in real applications, or if it was much better on any other chipsets up to that time.

---

The nVidia nForce can achieve much higher transfer rates because it actually has 2 separate 64-bit memory controllers and buses (ie dual channels), so it can truly read from 2 modules at the same time. It also interleaves the accesses, but the main improvement comes from the fact that there is 128-bits of total memory bus width available.
I'm not sure if this system is still a good representation of "interleaving" or not. It does implement interleaving, but it's most significant characteristic is the multi-channel architecture which dramatically increased the achievable transfer rate.

I was surprised to notice that nVidia's "TwinBank" paper says that the nForce supports 3.3v SDRAM memory. I don't think I've ever heard of an nForce board that actually had slots for it, but apparently it's possible. It's mentioned on page 6:
http://www.nvidia.com/attach/6160

Matth79 wrote:

The VIA chipsets had something that is called "interleave", but isn't - unlike 386 era interleave, which directed access to alternate banks, the VIA "interleave" allows a page to be held open in each bank.

The modern version is dual channel memory.

Yes, I think you are referring to the KT133A chipset.
VIA developed this because SDRAM only went up to 133 MHz, while the Athlon CPUs had 266 MHz FSB. By doing 4-way interleave, they could get nearly the same performance as systems with DDR memory.

According to this even SS7 chipsets supported interleaving.

alexanrs, thank you for sharing this. I am looking forward to testing it. I was unable to locate the downloadable file from that website, but located it here, http://www.georgebreese.com/net/dl0/venabler_v015.zip

You're welcome. I also plan on testing it on my Tually Celeron =)

alexanrs wrote:

According to this even SS7 chipsets supported interleaving.

I remember it being available on VIA MVP3 boards.