Anyone can tell me the exact purpose of the CRTC Mode Control Register and Underline Location Register's DIV2 and DIV4 bits?

I know that setting both of them (at least on the ET3000/ET4000) results in the planar position in memory be increased every half character clock (every 4 pixels). That would usually be useful for buffers only containing 4 pixels in 32-bits of VRAM(like the linear 8-bit modes mode 13h and mode 2Eh). But setting it to divide by 4(by only setting DIV4 and not DIV2) or 2(by only setting DIV2 and not DIV4) would result in the buffer being replicated 2 or 4 times on the screen(only grab next set of 32-bits once every 2 or 4 character clocks(equalling 16 pixels or 32 pixels))?