i am also interested in this, but it seems pretty difficult for someone to round so many chipsets together. also it may need a fast cpu(dx5-133 for example) to see the difference, which is unsupported on older boards.

also it depends on which tests you are going to run. dos benchmarks usually don't make use of video acceleration, making isa videocard a bottleneck which masks the difference.

From what I can tell, even the early 486 chipsets were pretty mature. The only important difference between old and new has to do with PCI and SRAM/DRAM strategies (like writeback, and interleaving)

Anonymous Coward wrote:

From what I can tell, even the early 486 chipsets were pretty mature. The only important difference between old and new has to do with PCI and SRAM/DRAM strategies (like writeback, and interleaving)

Well, this is what the thread should hopefully uncover. Anyone doing the test, will, of course have both the L2 caches set in write-through mode. To disable L2 cache interleave, simply use a single bank of cache. Personally, I have not seen any increase in benchmark results with cache interleave or not. And we all know that L2 in write-back mode shows very little improvement. Unfortunately, I no longer have any of these early 486 boards to test with.

Well, the Baby Screamer didn't even provide a boot screen, so 50 MHz is out.
Do you think the SiS Rabbit will cope with 50 MHz? Aside from the VLSI-based Baby Screamer, I have CHIPS 351/355/356, UMC 481/482, SiS Rabbit 310/320/330, and VIA 481/495. My SiS 460-based board uses a clock gen IC, so I cannot test 50 MHz on it. Since the VIA board is damn slow, I am guessing the timings are ultra conservative and that 50 MHz might work on it.

What minimum SRAM and DRAM speeds do I need for 50 MHz operation?

I doubt SiS Rabbit would work, because it's a true 386 chipset. The VIA 481/495 and the SiS460 are both designed for 486s, so they might work okay. On a 486, 12ns cache is ideally what you would want for 50MHz, but I've seen plenty of 40MHz 386 boards that use 20ns cache (with 15ns tag). RAM should be 60ns. Faster would be better, but it's basically unobtanium (even though 50ns reportedly exists). Of course, you may be able to do better if your board allows you to insert a lot of wait states. The biggest problem with designing the 50MHz motherboards was supposedly making sure everything was properly shielded due to problems with crosstalk (at least from what I can remember). I don't have much faith in a 50MHz 386. I would think even if you can make it stable, the wait states will kill the performance.

I accidently responded to the wrong thread. The last two posts, directly above this one, belong here: Re: Cyrix/Ti 486DLC vs 486SXL