MVP3 chipset uses 8bit tag ram so cacheable size = cache size * 256 if dirty bit is disabled (default) or cache size * 128 if dirty bit is enabled.
MVP3 doesn't support K7 CPU.

ironranger wrote:

I read an article on AnandTech that said all VP3 chipsets support 1GB cacheable memory area

Which article would that be?
It might if you use a CPU with L2 cache.

I suppose it was this article?

There's also a utility (can be found int this post) which shows the cacheable RAM. I don't know how correct results it gives, but until now it has always confirmed my theoretical expectations.

lazibayer wrote:

MVP3 chipset uses 8bit tag ram so cacheable size = cache size * 256 if dirty bit is disabled (default) or cache size * 128 if dirty bit is enabled.

So, 512KB * 256 or 128 would be 128MB or 64MB of cacheable memory area. What is a "dirty bit?" And, does this mean all MVP3 boards max out at 128MB of cacheable memory area? My board doesn't have any open areas to put anything in, so I'm assuming two tag ram modules, but again assuming those are the skinny long ones that look like they snap into place. What if somebody only has one?

Tetrium wrote:

Which article would that be? It might if you use a CPU with L2 cache. […]
Show full quote

ironranger wrote:

I read an article on AnandTech that said all VP3 chipsets support 1GB cacheable memory area

Which article would that be?
It might if you use a CPU with L2 cache.

I suppose it was this article?

Yes sir, that's the one.

As I said, I need the basics of how this stuff works because I'm not very advanced with it! I do remember hearing of the phrase "tag ram" 20 years ago, but I had no idea what it was. I didn't know there was a 64MB "barrier" back then and today I don't know how significant that is. If we're talking insignificant performance hits, then I don't have any problem throwing 512MB in either one of these boards. But, if they can't load windows in under 10 minutes, then I guess I'll have to keep it to their specific "barriers."

konc wrote:

There's also a utility (can be found int this post) which shows the cacheable RAM. I don't know how correct results it gives, but until now it has always confirmed my theoretical expectations.

I'll definitely check this out for the MVP board since that thing's up and running. But, what did people do when these things were new? I've read all sorts of reviews (like the AnandTech one) of these chipsets and boards that came with them and how they supposedly had impressive cacheable memory areas. And, also read some today that said without the board itself having tag ram modules, that they were no better than the ones that maxed out at 64MB, making them quite lame considering the high end dollar they must have commanded.

ironranger wrote:

So, 512KB * 256 or 128 would be 128MB or 64MB of cacheable memory area. What is a "dirty bit?" And, does this mean all MVP3 boards max out at 128MB of cacheable memory area? My board doesn't have any open areas to put anything in, so I'm assuming two tag ram modules, but again assuming those are the skinny long ones that look like they snap into place. What if somebody only has one?

MVP3 implements direct map cache scheme with 32byte line size, 8bit tag, and by default write back without dirty bit scheme as well. 512KB contains 16K such lines, so how do we know where these lines are mapped to the addresses in main memory? We need tag ram. How big? At least 16K x 8bit. Actually it's much more common to see 32k x 8bit tag ram chips onboard. Direct map without dirty bit roughly means the highest 8 bit of the address will be stored in the tag ram, while the lower 14 bit is mapped to the 16K lines in the cache. Total addressable lines: 2^(8+14) = 2^22; line size: 32byte; total addressable memory: 2^22 * 32 = 2^8 * 2^14 * 32 = 2^8 * 512KB = 256 * 512KB = 128MB. Or simply 256 * cache size.
Write back means once data is written to cache the writing job is considered done (by CPU). When a cache line is about to be evicted the chipset will write its content to main memory. But what if the cache line is intact? How do we know that and hence avoid redundant memory writing? We can cut one bit from the tag ram and call it dirty bit. The chipset now only writes the cache line back to memory if the dirty bit is set. Now we saved some memory writing but also halved the cacheable size.