keenerb wrote:

BloodyCactus wrote:

Ahh, yes. It is 4.77mhz according to schematic, the X1 input on the 8284 is tied directly to the 14.318 oscillator.

Yes, but the 8284 also has an EFI input, which comes from the oscillator and a F/!C input that I think selects between the two. The OSC output should always be based on the crystal, whereas the CLK output should depend on whether F/!C is high or low.

EDIT: Furthermore, F/!C is pulled high, so CLK is always derived from EFI. EFI is derived from U41,U31,etc which includes the turbo selection.

CLK is the processor speed, so ISA bus clock is still 4.77mhz as far as I can tell. F/!C must be what the CTRL=ALT=PLUS and turbo switch toggle for 4.77/turbo speeds.

*edit*

DMACLK seems to be derived from the 24mhz crystal though. I think DMA access could easily lock up the system with a 5mhz DMA controller?

keenerb wrote:

DMACLK seems to be derived from the 24mhz crystal though. I think DMA access could easily lock up the system with a 5mhz DMA controller?

I would think it could certainly malfunction. Whether that manifests as a lock-up, or failed DMA operations resulting in reported errors, I don't know.

As far as the ISA bus, while the OSC will be unaffected by Turbo, the CPU speed will affect memory and IO timings, won't it? Is the usual rule of thumb to increase wait states as CPU speed is increased? Do we just determine this experimentally? (I would assume this is where faster support chips could come in handy)

That's some super-speedy memory on the xi8088; wasn't most XT-class RAM 100 or 120ns? Maybe even 200ns? This is 55ns, I'd be surprised if wait states were needed for system memory. Although my knowledge is limited, maybe other things necessitate memory wait states...

*edit*

https://courses.engr.illinois.edu/ece390/book … H03/CH03-2.html

8088 memory access time (according to this random web page) is about 800ns, which our static ram should be more than capable of meeting, right?

Might still be needed for non-memory IO though, I suppose.

Now at 14 hours running Ultima III demo on loop, which (for me) is a recent record. There's no graphical corruption or any other issues apparent.

If it's still up and running after 24 hours the change from ALS to F logic on U39 may have had a positive impact. I'll repeat with my Malinov backplane and two additional cards installed (Floppy and multi-IO card) and see how it runs.

*edit*

U39 is providing the CLK signal to the entire ISA bus, right? I'm assuming that the more cards you have on the bus, the greater the power requirements for the CLK signal become, and that's why a high output current chip is desired?

That might explain why certain combinations of cards are problematic, or why adding that one last adapter causes lockups.

While everyone's waiting on parts and/or time, here's something really interesting that popped up when googling Sergey stuff:

http://www.malinov.com/Home/sergeys-projects/xi-8088-cpld

Apparently Sergey had a hidden page detailing a CPLD version of his xi8088 board. Just prototype/planning stages as of 2012 but still really neat...

keenerb wrote:

U39 is providing the CLK signal to the entire ISA bus, right? I'm assuming that the more cards you have on the bus, the greater the power requirements for the CLK signal become, and that's why a high output current chip is desired?

Yes, but many cards on the bus don't use the CLK signal. In particular, the simple 8255 card that I have doesn't use it, and that card has a significant impact on stability.

The schematic for Sergey's FDC+Serial card doesn't show CLK being used. It does, however, use RESETDRV, and RESETDRV is also derived from U39.

hopefully I can do some bus probing this weekend and see what the bus signals look like, maybe some of the signals are right on the timing window like ALE/AEN or something.

I've noticed on mine, I have dos6.22 and have the config.sys menu thing, on that screen, it never locks up. i can f5 to bypass all config.sys/auto, load absoultely zero, its ok for a time but will get like a stack overflow of something somewhere. some random dos error message.

loading anything is insta lockup.

so were fine with low memory references (and seemingly memory on the bus like text video ram segment). but that still doesnt fit right with me.

I've only probed the OSC pin so far, so I'll check the CLK pin and see its stability in relation to OSC.

I did find this:

http://www.os2museum.com/wp/the-isa-osc-mystery/

His OSC signal looks like your CLK signal, which looks nothing like your OSC.

His OSC also seems to be peaking around 2v from the absolutely minimum, if the "Y1=200mV" on his screen means one Y increment = 200mv value.

I have some images to share. First one is a baseline of the 5V line on the ISA bus.

Next is my Xi 8088 with 5 cards installed (CF, CPU, VGA, Adlib, Floppy). From top to bottom these are MEMR (yellow), CLK (turqoise), A0 (purple), D0 (blue):

Next we add the 8255 card:

Finally we add both the 8255 and my CP/M coprocessor:

I haven't really had a chance to digest these yet (it's dinner time!). Stability becomes progressively worse from the 5 card to the 6 card and 7 card configurations.

I don't know if those are good or bad but they seem fairly consistent, at least. My guess would be that they look good.

I finished 24 hours of Ultima 3 with no issues. I switched back to an 8 slot backplane and added some additional cards. We will see what happens

those data + address bus lines look noisy as all get up.

Certainly all the lines show lot of ringing.

I have my isa prototype board out, will try and solder some header pins to it.

I'm wondering if some very small caps will reduce the ringing and add stability

smbaker wrote:

Finally we add both the 8255 and my CP/M coprocessor:

I want to know on the cp/m coprocessor! (maybe this isnt the thread tho). I thought of making an isa card with a z80 + sram on it, have some directio isa bus io from the x86... anyway. off topic!

After adding two previously unused cards, memory tests immediately started failing after just a few repititions.

I'm trying with just the three original cards in the new backplane.

Sergey has mentioned to me several times that the ram is unbuffered/directly attached to ISA bus(?), and he thinks that may be one of the reasons we see lockups.

"My suspicion is that SRAM and Flash ROM ICs can't handle much load, so putting them behind a bus transceiver should improve the situation."

Should it be possible to use an ISA memory card like the Lotech 1MB board for main system memory? I removed the two memory chips and tried, but the system gave the main memory failure beeps.

I also put my xt-ide adapter on the farthest slot from my xi8088 processor board, just in case that has anything to do with the problem.

Another picture, this one with my prototype bus terminator, which uses a 1K resistor to 5V and a 680 ohm resistor to ground for each line:

I think it cleaned up MEMR, but it made D0 look a little bit uglier. The 1K/680 resistor network will pull any high-impedance signal to ~ 2V, so that's why we see D0 spending a lot of time at the halfway point.

I would think we could use the Lotech memory card, since it's SRAM based, just like the Xi 8088. It could be the reason why your traditional memory card isn't working is that we're missing some of the DRAM refresh logic. I'm not really sure, I don't have much experience with dynamic RAM, only SRAM. The LoTech card would be a good thing to try. It's possible we could also design a small piggyback board for the Xi 8088 that put the SRAM data lines behind a buffer.

As far as the CP/M coprocessor, it's a "UniDOS coprocessor card". It has a Z80, some RAM, and about a half dozen logic chips on it. It comes with software that loads a CP/M program into the RAM and then starts executing it, sending console IO, file IO, and such to the PC's BIOS. It's pretty cool.

Another picture with the terminator board, zoomed out a bit further:

Here it's easy to see how the terminator has caused D0 to have a high, a low, and a middle. I'm kinda surprised that it works with the signal looking as awful as it does... but it's humming away running checkit.

BloodyCactus: Regarding adding capacitors, one of the links I came across when looking into ISA bus termination described a strategy of using a capacitor and a resistor network (https://www.electronicspoint.com/threads/isa- … uestion.113863/):

As in the ISA standard, the recommended network consists of a resistor- capacitor network of 40- 60 ohms in series with 30-70 pF […]
Show full quote

As in the ISA standard, the recommended network consists of a resistor-
capacitor network of 40-
60 ohms in series with 30-70 pF, connected between each bus signal and
ground.

In my bus termination research, I came across three termination strategies -- resistor networks to 5V/GND, resistor-capacitor networks, and a resistor network to a regulated 2.7 V supply ("S100 active terminator).

Ran checkit all night, no errors with just the three cards.

Any more than three cards and everything is toast.

I wonder what's keeping my lo-tech 1mb card from working, that seems to be the next logical step for me to troubleshoot, at least. I don't understand your fancy graphs and capacitors and all that...

So, the schematic has a bunch of memory-related data (unsurprisingly). All the lines connected to the memory/flash are standard ISA signals except the RAM2_CS line, which simply tells which chip should be active.

The ISA card is attached to the same signals on the bus, so it should basically behave identically, shouldn't it? Something else on the card must be screwing things up, or my card has an issue with first 64kb of memory. I noticed with card installed/configured AND on-board memory enabled the memory test fails at 64kb, so maybe I'm doing something wrong with my lo-tech card.

I don't see anything that should prevent the lo-tech card from working. The lo-tech card is just the very same SRAM chips, with a data buffer, and some address selection logic. The Lo-Tech board seems like it would be the easiest way for us to narrow down the problem to whether or not it's lack of RAM buffering that is the issue.

I did get a fairly long run last night with my bus terminator board installed, but it did still lock up at some point during the night.

Scott

Another thing we could try doing would be to select a different SRAM chip. AS6C4008 is 55ns, and performance data is given for VOH and VOL at -1ma and 2ma. CY7C1049G-10VXI is 10ns and performance data is given for VOH and VOL at -4ma and 8ma. Four times as much. That's not to say that the AS6C4008 isn't capable of more drive current, but that's what the manufacturer tested the chips at.

Unfortunately the CY7C1049G-10VXI is a SMD device, and we'd have to come up with a breakout board.