386DX will always perform instruction fetches using 32-bit accesses, even when running 16-bit code. This means it should still outperform the 386SX, though how much will depend on exactly what benchmark is being used.

I've got a 386SX 25. What bench should-I run ?

I had a cacheless 386DX20 Hyundai PC and I compared it against a Headland 286/16 PC I had at the time. The 386 was marginally better , I used the same VGA in both machines and Wolf3D for example was 1 or 2 frames better at best. I don't think I kept the results though as I gave away the 386DX after that.

Did the tests years ago. But 386DX with caches disabled was slower then 386SX on the same speed.

Not sure if anyone noticed my other post, but I claimed that on 20 or 25MHz 386s, cache isn't really necessary if you use high quality memory with optimal timings. A 386DX should still be a little faster than a 386SX if the memory is tuned the same way. Maybe the 386DX you tested with cache disabled was using slow DRAM.

The SX may have been a lousy chip, but some 386SX machines were also combined with late, powerful 286 chipsets.
These had got advanced features, like options for wait-states, EMS, shadow memory, interleaving, etc.

In memory access, a 386sx with 4 30 pin SIMMs in 2 bank interleave would be about the same as a 386DX with 4 30 pin SIMMs in a single 32 bit bank - to give the DX the upper hand, it would need two full banks

My 386SX25 let me tweak the timings. That way I get a score of 4.3x in speedsys IIRC

I don't agree that the 386SX was a lousy chip. Internally it was identical to the DX. The 24-bit memory addressing at the time was a complete non-issue, since many 386DX systems did not support over 16MB anyway. Sometimes they didn't even work properly with more than 12MB. The 16-bit path to memory aslo wasn't too bad as long as you had bank interleaving and a little cache (which wasn't all that common since the SX was aimed at budget systems). The 16-bit datapath also allowed you to install memory in pairs, rather than in sets for four, which gave you more flexability for memory expansion.

Anonymous Coward wrote:

I don't agree that the 386SX was a lousy chip. Internally it was identical to the DX. The 24-bit memory addressing at the time was a complete non-issue

It was almost identical... physically missing were the 8 addressing lines required to be a DX. In reality as no motherboards/chipsets supported 24-bit addressing, the SX had to rest as a 16-bit CPU... the other 8 address lines to make up the 24 were useless and redundant.

SX systems at the time were marketed and aimed at residential/home use, at the same time DX CPU's were found in servers and other high end industry systems. Gradually though the DX found it's way into homes.

From experiences it seems in reality there is not much real-world difference without cache but it would still be interesting to see the bench-marking and the difference in memory transfer speed between a 16-bit bus 386 and 32-bit bus 386, with all things equal... more specifically the clock i.e. 33MHz for both.

386_junkie wrote:

Anonymous Coward wrote:

I don't agree that the 386SX was a lousy chip. Internally it was identical to the DX. The 24-bit memory addressing at the time was a complete non-issue

It was almost identical... physically missing were the 8 addressing lines required to be a DX. In reality as no motherboards/chipsets supported 24-bit addressing, the SX had to rest as a 16-bit CPU... the other 8 address lines to make up the 24 were useless and redundant.

Think you're getting address and data lines confused! 386SX motherboards do support 24-bit addressing, 16-bit addressing would leave you with a total of 64kb memory...

It's possible that some might not decode all 24 bits, but certainly more than 16.

SarahWalker wrote:

386_junkie wrote:

Anonymous Coward wrote:

I don't agree that the 386SX was a lousy chip. Internally it was identical to the DX. The 24-bit memory addressing at the time was a complete non-issue

It was almost identical... physically missing were the 8 addressing lines required to be a DX. In reality as no motherboards/chipsets supported 24-bit addressing, the SX had to rest as a 16-bit CPU... the other 8 address lines to make up the 24 were useless and redundant.

Think you're getting address and data lines confused! 386SX motherboards do support 24-bit addressing, 16-bit addressing would leave you with a total of 64kb memory...

It's possible that some might not decode all 24 bits, but certainly more than 16.

I was talking about both... memory and data: -

"It was almost identical... physically missing were the 8 addressing lines required to be a DX."... Memory addressing

"In reality as no motherboards/chipsets supported 24-bit addressing, the SX had to rest as a 16-bit CPU... the other 8 address lines to make up the 24 were useless and redundant."... Data lines

Internally there are 24 data lines in an SX... but only have 16 pins exposed... also motherboards can't address over 24 data lines.

Internally there are 24 data lines in an SX... but only have 16 pins exposed... also motherboards can't address over 24 data lines.

This is not correct. Internally, the SX has 32 address lines, but only 24 are connected.

Also, the SX is not a 16-bit CPU. It runs 32-bit software.

Ok, stop the bus... I've checked this out for my own sanity.

http://www.cpu-collection.de/?tn=0&l0=co&l1=I … 0SX#NG80386SX33

There are two roads (bus systems) in and out of this CPU... a data bus, and a separate address bus.

The SX CPU does have a 32-bit core (I realize this now), but can only manipulate 16-bit word at any time over the 16 pins that are connected to the data bus (hence needing only 2 x 30 pin simms!). I somehow managed to interchange the number 24 to the number of internal data lines from the number of addressing lines. Internally with a 32-bit core, it could in theory register and manipulate 32-bits (data lines, not addressing!) but only has 16 pins available to transmit and receive bits across the 16-bit data bus.

My mistake was in thinking that internally it could manipulate 24-bits of data at a time... giving rise the theory of using 3 x 30 pin simms... which would just be madness.