1F000:00000457 B0 01 movb al,01
2F000:00000459 BA 84 00 movw dx,0084
3F000:0000045C EE out dx,al
4F000:0000045D 66 B8 01 00 00 80 movd eax,80000001
5F000:00000463 66 F7 E8 imuld eax
6F000:00000466 66 B8 11 22 33 44 movd eax,44332211
7F000:0000046C 66 89 C3 movd ebx,eax
8F000:0000046F 66 B9 55 66 77 88 movd ecx,88776655
9F000:00000475 66 F7 E1 muld ecx
1000:01:34:77.07472: Interrupt 00=0000:00000000@F000:0478(F7); ERRORCODE: -1
11F000:00000478 66 F7 F1 divd ecx
120000:00000000 00 00 addb [ds:bx+si],al

1extern byte tmps,tmpp; //Sign/parity backup!
2
3extern byte CPU_databussize; //Current data bus size!
4
5extern byte tempAL;
6uint_32 tempEAX;
7uint_64 tempEDXEAX;
8
9OPTINLINE void op_div32(uint_64 valdiv, uint_32 divisor) {
10	//word v1, v2;
11	if ((!divisor) && (CPU[activeCPU].internalinstructionstep==0)) //First step?
12	{
13		//Timings always!
14		++CPU[activeCPU].internalinstructionstep; //Next step after we're done!
15		CPU[activeCPU].cycles_OP += 1; //Take 1 cycle only!
16		CPU[activeCPU].executed = 0; //Not executed yet!
17		return;
18	}
19	uint_32 quotient, remainder; //Result and modulo!
20	byte error, applycycles; //Error/apply cycles!
21	CPU80386_internal_DIV(valdiv,divisor,&quotient,&remainder,&error,32,2,6,&applycycles); //Execute the unsigned division! 8-bits result and modulo!
22	if (error==0) //No error?
23	{
24		REG_EAX = quotient; //Quotient!
25		REG_EDX = remainder; //Remainder!
26	}
27	else //Error?
28	{
29		CPU_exDIV0(); //Exception!
30		return; //Exception executed!
31	}
32	if (applycycles) /* No 80286+ cycles instead? */
33	{
34		if (MODRM_EA(params)) //Memory?
35		{
36			CPU[activeCPU].cycles_OP += 6 - EU_CYCLES_SUBSTRACT_ACCESSREAD; //Mem max!
37		}
38	}
39	}

1//Universal DIV instruction for x86 DIV instructions!
2/*
3
4Parameters:
5	val: The value to divide
6	divisor: The value to divide by
7	quotient: Quotient result container
8	remainder: Remainder result container
9	error: 1 on error(DIV0), 0 when valid.
10	resultbits: The amount of bits the result contains(16 or 8 on 8086) of quotient and remainder.
11	SHLcycle: The amount of cycles for each SHL.
12	ADDSUBcycle: The amount of cycles for ADD&SUB instruction to execute.
13
14*/
15void CPU80386_internal_DIV(uint_64 val, uint_32 divisor, uint_32 *quotient, uint_32 *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles)
16{
17	uint_64 temp, temp2, currentquotient; //Remaining value and current divisor!
18	byte shift; //The shift to apply! No match on 0 shift is done!
19	temp = val; //Load the value to divide!
20	*applycycles = 1; //Default: apply the cycles normally!
21	if (divisor==0) //Not able to divide?
22	{
23		*quotient = 0;
24		*remainder = temp; //Unable to comply!
25		*error = 1; //Divide by 0 error!
26		return; //Abort: division by 0!
27	}
28
29	if (CPU_apply286cycles()) /* No 80286+ cycles instead? */
30	{
31		SHLcycle = ADDSUBcycle = 0; //Don't apply the cycle counts for this instruction!
32		*applycycles = 0; //Don't apply the cycles anymore!
33	}
34
35	temp = val; //Load the remainder to use!
36	*quotient = 0; //Default: we have nothing after division! 
37	nextstep:
38	//First step: calculate shift so that (divisor<<shift)<=remainder and ((divisor<<(shift+1))>remainder)
39	temp2 = divisor; //Load the default divisor for x1!
40	if (temp2>temp) //Not enough to divide? We're done!
41	{
42		goto gotresult; //We've gotten a result!
43	}
44	currentquotient = 1; //We're starting with x1 factor!
45	for (shift=0;shift<(resultbits+1);++shift) //Check for the biggest factor to apply(we're going from bit 0 to maxbit)!
46	{
47		if ((temp2<=temp) && ((temp2<<1)>temp)) //Found our value to divide?
48		{
49			CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 more SHL cycle for this!
50			break; //We've found our shift!
51		}
52		temp2 <<= 1; //Shift to the next position!
53		currentquotient <<= 1; //Shift to the next result!
54		CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 SHL cycle for this! Assuming parallel shifting!
55	}
56	if (shift==(resultbits+1)) //We've overflown? We're too large to divide!
57	{
58		*error = 1; //Raise divide by 0 error due to overflow!
59		return; //Abort!
60	}

61	//Second step: substract divisor<<n from remainder and increase result with 1<<n.
62	temp -= temp2; //Substract divisor<<n from remainder!
63	*quotient += currentquotient; //Increase result(divided value) with the found power of 2 (1<<n).
64	CPU[activeCPU].cycles_OP += ADDSUBcycle; //We're taking 1 substract and 1 addition cycle for this(ADD/SUB register take 3 cycles)!
65	goto nextstep; //Start the next step!
66	//Finished when remainder<divisor or remainder==0.
67	gotresult: //We've gotten a result!
68	if (temp>((1<<resultbits)-1)) //Modulo overflow?
69	{
70		*error = 1; //Raise divide by 0 error due to overflow!
71		return; //Abort!		
72	}
73	if (*quotient>((1<<resultbits)-1)) //Quotient overflow?
74	{
75		*error = 1; //Raise divide by 0 error due to overflow!
76		return; //Abort!		
77	}
78	*remainder = temp; //Give the modulo! The result is already calculated!
79	*error = 0; //We're having a valid result!
80}

163                                  ;
2    64                                  ;   We set our exception handlers at fixed addresses to simplify interrupt gate descriptor initialization.
3    65                                  ;
4    66                                  OFF_INTDEFAULT   equ OFF_ERROR
5    67                                  OFF_INTDIVERR    equ OFF_INTDEFAULT+0x200
6    68                                  OFF_INTPAGEFAULT equ OFF_INTDIVERR+0x200
7    69                                  OFF_INTBOUND     equ OFF_INTPAGEFAULT+0x200
8    70                                  
9    71                                  ;
10    72                                  ;   Output a byte to the POST port, destroys al and dx
11    73                                  ;
12    74                                  %macro POST 1
13    75                                  	mov al, 0x%1
14    76                                  	mov dx, POST_PORT
15    77                                  	out dx, al
16    78                                  %endmacro
17    79                                  
18    80                                  
19    81                                  header:
20    82 00000000 746573743338362E61-     	db COPYRIGHT
21    82 00000009 736D20284329203230-
22    82 00000012 31322D32303135204A-
23    82 0000001B 65666620506172736F-
24    82 00000024 6E732C202843292032-
25    82 0000002D 303137204D6172636F-
26    82 00000036 20426F72746F6C696E-
27    82 0000003F 202020202020       
28    83                                  
29    84                                  cpuTest:
30    85 00000045 FA                      	cli
31    86                                  
32    87                                  
33    88                                  ; ==============================================================================
34    89                                  ;	Real mode tests
35    90                                  ; ==============================================================================
36    91                                  
37    92                                  ;
38    93                                  ;   Conditional jumps
39    94                                  ;
40    95                                  %include "tests/jcc_m.asm"
41     1                              <1> ;
42     2                              <1> ; Tests conditional relative jumps.
43     3                              <1> ; Uses: AX, ECX, Flags
44     4                              <1> ;
45     5                              <1> ; Opcodes tested, with positive and negative offsets:
46     6                              <1> ;
47     7                              <1> ; rel8  rel16/32 mnemonic condition
48     8                              <1> ; 70    0F80     JO       OF=1
49     9                              <1> ; 71    0F81     JNO      OF=0
50    10                              <1> ; 72    0F82     JC       CF=1
51    11                              <1> ; 73    0F83     JNC      CF=0
52    12                              <1> ; 74    0F84     JZ       ZF=1
53    13                              <1> ; 75    0F85     JNZ      ZF=0
54    14                              <1> ; 76    0F86     JBE      CF=1 || ZF=1
55    15                              <1> ; 77    0F87     JA       CF=0 && ZF=0
56    16                              <1> ; 78    0F88     JS       SF=1
57    17                              <1> ; 79    0F89     JNS      SF=0
58    18                              <1> ; 7A    0F8A     JP       PF=1
59    19                              <1> ; 7B    0F8B     JNP      PF=0
60    20                              <1> ; 7C    0F8C     JL       SF!=OF

61    21                              <1> ; 7D    0F8D     JNL      SF=OF
62    22                              <1> ; 7E    0F8E     JLE      ZF=1 || SF!=OF
63    23                              <1> ; 7F    0F8F     JNLE     ZF=0 && SF=OF
64    24                              <1> ; E3             JCXZ     CX=0
65    25                              <1> ; E3             JECXZ    ECX=0
66    26                              <1> ;
67    27                              <1> %macro testJcc 1
68    28                              <1> 	mov    ah, PS_CF
69    29                              <1> 	sahf         ; don't use the stack (pushf/popf)
70    30                              <1> 	jnc   %%err1 ; 73 / 0F83   JNC  CF=0
71    31                              <1> 	jc    %%jcok ; 72 / 0F82   JC   CF=1
72    32                              <1> 	hlt
73    33                              <1> %%jz:
74    34                              <1> 	mov    ah, PS_ZF
75    35                              <1> 	sahf
76    36                              <1> 	jnz   %%err1 ; 75 / 0F85   JNZ  ZF=0
77    37                              <1> 	jz    %%jzok ; 74 / 0F84   JZ   ZF=1
78    38                              <1> 	hlt
79    39                              <1> %%jp:
80    40                              <1> 	mov    ah, PS_PF
81    41                              <1> 	sahf
82    42                              <1> 	jnp   %%err1 ; 7B / 0F8B   JNP  PF=0
83    43                              <1> 	jp    %%jpok ; 7A / 0F8A   JP   PF=1
84    44                              <1> 	hlt
85    45                              <1> %%js:
86    46                              <1> 	mov    ah, PS_SF
87    47                              <1> 	sahf
88    48                              <1> 	jns   %%err1 ; 79 / 0F89   JNS  SF=0
89    49                              <1> 	js    %%jsok ; 78 / 0F88   JS   SF=1
90    50                              <1> 	hlt
91    51                              <1> %%jna:
92    52                              <1> 	mov    ah, PS_ZF|PS_CF
93    53                              <1> 	sahf
94    54                              <1> 	ja    %%err1  ; 77 / 0F87   JA   CF=0 && ZF=0
95    55                              <1> 	jna   %%jnaok ; 76 / 0F86   JBE  CF=1 || ZF=1
96    56                              <1> %%next1:
97    57                              <1> 	jmp %%jnc
98    58                              <1> 
99    59                              <1> %if %1==16
100    60                              <1> 	times  128 hlt
101    61                              <1> %endif
102    62                              <1> 
103    63                              <1> %%err1:
104    64                              <1> 	hlt
105    65                              <1> 
106    66                              <1> ; test negative offsets
107    67                              <1> %%jcok:   jc   %%jz
108    68                              <1> %%jzok:   jz   %%jp
109    69                              <1> %%jpok:   jp   %%js
110    70                              <1> %%jsok:   js   %%jna
111    71                              <1> %%jnaok:  jna  %%next1
112    72                              <1> 

1testLEA32 [eax * 2], 0x00000002

1testLEA32 [ebx * 4], 0x00000008

10010:00000F96 50 pushd eax
20010:00000F97 8D 04 00 lead eax,[ds:eax+eax*1]
30010:00000F9A 83 F8 02 cmpd eax,0002
40010:00000F9D 0F 85 5D B0 00 00 jne 0000c000
50010:00000FA3 58 popd eax
60010:00000FA4 50 pushd eax
70010:00000FA5 8D 04 9D lead eax,[ds:00000000+ebx*4]
80010:00000FA8 00 00 addb [ds:eax],al
90010:00000FAA 00 00 addb [ds:eax],al
100010:00000FAC 83 F8 08 cmpd eax,0008
110010:00000FAF 0F 85 4B B0 00 00 jne 0000c000
120010:00000FB5 58 popd eax
130010:00000FB6 50 pushd eax
140010:00000FB7 8D 04 CD lead eax,[ds:00000000+ecx*8]
150010:00000FBA 00 00 addb [ds:eax],al
160010:00000FBC 00 00 addb [ds:eax],al
170010:00000FBE 83 F8 20 cmpd eax,0020
180010:00000FC1 0F 85 39 B0 00 00 jne 0000c000
190010:00000FC7 58 popd eax
200010:00000FC8 50 pushd eax
210010:00000FC9 8D 44 00 40 lead eax,[ds:40+eax+eax*1]
220010:00000FCD 83 F8 42 cmpd eax,0042
230010:00000FD0 0F 85 2A B0 00 00 jne 0000c000
240010:00000FD6 58 popd eax
250010:00000FD7 50 pushd eax
260010:00000FD8 8D 04 9D lead eax,[ds:00000000+ebx*4]
270010:00000FDB 40 incd eax
280010:00000FDC 00 00 addb [ds:eax],al
2900:10:11:29.04144: #GP fault(00000018)!
300010:00000FDE 00 83 F8 48 0F 85 addb [ds:ebx+850f48f8],al
310010:0000C000 FA cli
320010:0000C001 F4 hlt
330010:0000C002 F4 <hlt>