One bus cycle takes several clocks to complete on ISA. On older CPUs it is directly tied to CPU's own bus cycles which are 4 clocks long usually : ((3.579545 * 4) / 3) = XT CPU speed / (4 clocks per bus cycle + 1 wait state) = ~954545 bytes/second

Interesting info!

Another limiting factor is that CPU can only write one/two bytes at a time, and it has to fetch instructions between those writes too so actual theoretical figures are unreachable on stuff like the XT.

Sounds reasonable. Well, with 16 bit writes my 286 more or less gets the theoretical maximum when pushing simple data to the Tseng VGA card.

Also, I guess bus mastering cards would have been able to achieve this throughput.

Sounds indeed interesting! If I was nitpicking, I'd say that the PC/AT had no ISA bus yet, but an AT bus. 😉
ISA came later and capped the bus speed at ~8MHz. Before that standardization, bus speeds of 10 or 12MHz weren't that uncommon.
(That's why a few expansion cards from the mid-late 80s could go along with higher speeds, but several cards from the 90s couldn't.)