Looking at the other values (256KB -> 8K, 512KB -> 32K (Probably 16K used)) then 1M -> 32K looks logical.

Yes it looks like logical, but I've never seen before. I have the impression it's necessary more memory (TAG) to control that amount of cache(1MB)

TAG size determines how much RAM is cacheable, with a small chip (if the conf works) you might only have small part of the memory cacheable and anything beyond will be very slow compared to cacheable region. You want the TAG to be as large as possible and often faster than other SRAMs to ensure things work at tighter timings.

Tiido wrote:

TAG size determines how much RAM is cacheable, with a small chip (if the conf works) you might only have small part of the memory cacheable and anything beyond will be very slow compared to cacheable region. You want the TAG to be as large as possible and often faster than other SRAMs to ensure things work at tighter timings.

I always thought that cacheable ram amount was determined by how many bits the tag chip has because it defines the address range of the memory that is cached and not the size if it is 32k or 64k.

http://www.pcguide.com/ref/mbsys/cache/charCa … eability-c.html

Right, width is what matters on that regard, size is needed to actually map all the cache lines/blocks into the actual cache memory. Large cache size needs a large TAG. I'm not totally sure how the actual implementations work on most chipsets but size of TAG impacts the size of cache lines/blocks in the cache and in theory a small TAG can still work with large cache that holds large blocks/lines.

The Pentium uses a larger cache line than the 486, so it does not use as many entries