While there is no more answers for my questions above I almost finished PCB layout.

Here are some steps of refining:

- refined layout;
- added power bypass capacitor for AY;
- oriented all electrolytic capacitors in the same way (for consistency and ease of assembly);
- replaced LM386 power amplifiers with a good quality standard stereo opamp output buffer for line out;
- replaced "5 isolated resistors" resistor network and two separate 10k resistors with two "7 bussed resistors" networks, the same one that are used for joystick inputs (decreased BOM list, more easy assembly).

Basically, layout is done. Will it work flawlessly? Who knows, prototype production run will tell. I think I'll make some more iterations of refining and checking the layout and then I'll order first prototypes. 🙄

The last thing to do - to get working firmware for the GAL chip. I'm curious to know about progress at that.
If nothing helps, I think I can try to "read" GAL my ways. Like, attaching logic analyzer to control outputs of GAL and some address/data lines and run some games that support this card and get information about what ports are each of the components are, how GAL controlls AY in regards of ports and read/write operations.
So, if there is low or no progress on GAL reading, I want to offer moturimi1 an option to send GAL to me to try it. Obviously I can not do anything more with this card, because it will not work without the GAL.

I've got some help from the programmer called Cerenas.
Here are some hooked DOSBox dumps with some games that support CSM:

1DOSBox version 0.74-2-vs2017
2Copyright 2002-2018 DOSBox Team, published under GNU GPL.
3---
4SDL_Init: Starting up with SDL windib video driver.
5          Try to update your video card and directx drivers!
6CONFIG:Loading primary settings from config file dosbox.conf
7Maximum memory size is 63 MB
8Memory sizes above 31 MB are NOT recommended.
9Stick with the default values unless you are absolutely certain.
10MIDI:Opened device:win32
11[CSM] Covox Sound Master hooks installed
12[CSM] Write on port 223h, len 1, val 0h
13[CSM] Write on port 220h, len 1, val dh
14[CSM] Read on port 221h, len 1
15[CSM] Write on port 220h, len 1, val dh
16[CSM] Write on port 221h, len 1, val adh
17[CSM] Read on port 221h, len 1
18[CSM] Write on port 220h, len 1, val eh
19[CSM] Write on port 221h, len 1, val 0h
20[CSM] Read on port 221h, len 1
21[CSM] Write on port 220h, len 1, val fh
22[CSM] Write on port 221h, len 1, val e0h
23[CSM] Read on port 221h, len 1
24[CSM] Write on port 220h, len 1, val 7h
25[CSM] Write on port 221h, len 1, val ffh
26[CSM] Read on port 221h, len 1
27[CSM] Write on port 220h, len 1, val eh
28[CSM] Write on port 221h, len 1, val 0h
29[CSM] Read on port 221h, len 1
30[CSM] Write on port 220h, len 1, val 0h
31[CSM] Write on port 221h, len 1, val 0h
32[CSM] Read on port 221h, len 1
33[CSM] Write on port 220h, len 1, val 1h
34[CSM] Write on port 221h, len 1, val 0h
35[CSM] Read on port 221h, len 1
36[CSM] Write on port 220h, len 1, val 2h
37[CSM] Write on port 221h, len 1, val 0h
38[CSM] Read on port 221h, len 1
39[CSM] Write on port 220h, len 1, val 3h
40[CSM] Write on port 221h, len 1, val 0h
41[CSM] Read on port 221h, len 1
42[CSM] Write on port 220h, len 1, val 4h
43[CSM] Write on port 221h, len 1, val 0h
44[CSM] Read on port 221h, len 1
45[CSM] Write on port 220h, len 1, val 5h
46[CSM] Write on port 221h, len 1, val 0h
47[CSM] Read on port 221h, len 1
48[CSM] Write on port 220h, len 1, val 6h
49[CSM] Write on port 221h, len 1, val 0h
50[CSM] Read on port 221h, len 1
51[CSM] Write on port 220h, len 1, val 7h
52[CSM] Write on port 221h, len 1, val 0h
53[CSM] Read on port 221h, len 1
54[CSM] Write on port 220h, len 1, val 8h
55[CSM] Write on port 221h, len 1, val 0h
56[CSM] Read on port 221h, len 1
57[CSM] Write on port 220h, len 1, val 9h
58[CSM] Write on port 221h, len 1, val 0h
59[CSM] Read on port 221h, len 1
60[CSM] Write on port 220h, len 1, val ah

61[CSM] Write on port 221h, len 1, val 0h
62[CSM] Read on port 221h, len 1
63[CSM] Write on port 220h, len 1, val bh
64[CSM] Write on port 221h, len 1, val 0h
65[CSM] Read on port 221h, len 1
66[CSM] Write on port 220h, len 1, val ch
67[CSM] Write on port 221h, len 1, val 0h
68[CSM] Read on port 221h, len 1
69[CSM] Write on port 220h, len 1, val dh
70[CSM] Write on port 221h, len 1, val 0h
71[CSM] Read on port 221h, len 1
72[CSM] Write on port 220h, len 1, val dh
73[CSM] Read on port 221h, len 1
74[CSM] Write on port 220h, len 1, val dh
75[CSM] Write on port 221h, len 1, val bdh
76[CSM] Read on port 221h, len 1
77[CSM] Write on port 220h, len 1, val 0h
78[CSM] Write on port 221h, len 1, val 0h
79[CSM] Read on port 221h, len 1
80[CSM] Write on port 220h, len 1, val 1h
81[CSM] Write on port 221h, len 1, val 0h
82[CSM] Read on port 221h, len 1
83[CSM] Write on port 220h, len 1, val 2h
84[CSM] Write on port 221h, len 1, val 0h
85[CSM] Read on port 221h, len 1
86[CSM] Write on port 220h, len 1, val 3h
87[CSM] Write on port 221h, len 1, val 0h
88[CSM] Read on port 221h, len 1
89[CSM] Write on port 220h, len 1, val 4h
90[CSM] Write on port 221h, len 1, val 0h
91[CSM] Read on port 221h, len 1
92[CSM] Write on port 220h, len 1, val 5h
93[CSM] Write on port 221h, len 1, val 0h
94[CSM] Read on port 221h, len 1
95[CSM] Write on port 220h, len 1, val 6h
96[CSM] Write on port 221h, len 1, val 0h
97[CSM] Read on port 221h, len 1
98[CSM] Write on port 220h, len 1, val 7h
99[CSM] Write on port 221h, len 1, val 0h
100[CSM] Read on port 221h, len 1
101[CSM] Write on port 220h, len 1, val 8h
102[CSM] Write on port 221h, len 1, val 0h
103[CSM] Read on port 221h, len 1
104[CSM] Write on port 220h, len 1, val 9h
105[CSM] Write on port 221h, len 1, val 0h
106[CSM] Read on port 221h, len 1
107[CSM] Write on port 220h, len 1, val ah
108[CSM] Write on port 221h, len 1, val 0h
109[CSM] Read on port 221h, len 1
110[CSM] Write on port 220h, len 1, val fh
111[CSM] Write on port 221h, len 1, val 0h
112[CSM] Read on port 221h, len 1
113[CSM] Write on port 220h, len 1, val dh
114[CSM] Read on port 221h, len 1
115[CSM] Write on port 220h, len 1, val dh
116[CSM] Write on port 221h, len 1, val dh
117[CSM] Read on port 221h, len 1
118[CSM] Write on port 220h, len 1, val 7h
119[CSM] Write on port 221h, len 1, val ffh
120[CSM] Read on port 221h, len 1
121[CSM] Write on port 220h, len 1, val dh
122[CSM] Read on port 221h, len 1
123[CSM] Write on port 220h, len 1, val dh
124[CSM] Write on port 221h, len 1, val adh
125[CSM] Read on port 221h, len 1
126[CSM] Write on port 220h, len 1, val eh
127[CSM] Write on port 221h, len 1, val aah
128[CSM] Read on port 221h, len 1
129[CSM] Write on port 222h, len 1, val 88h
130[CSM] Write on port 222h, len 1, val 88h
131[CSM] Write on port 222h, len 1, val 8ah
132[CSM] Write on port 222h, len 1, val 86h
133[CSM] Write on port 222h, len 1, val 8ch
134[CSM] Write on port 222h, len 1, val 90h
135...

1[CSM] Covox Sound Master hooks installed
2[CSM] Write on port 220h, len 1, val 7h
3[CSM] Write on port 221h, len 1, val ffh
4[CSM] Read on port 221h, len 1
5[CSM] Write on port 220h, len 1, val eh
6[CSM] Write on port 221h, len 1, val 22h
7[CSM] Read on port 221h, len 1
8[CSM] Write on port 220h, len 1, val eh
9[CSM] Read on port 221h, len 1
10[CSM] Write on port 220h, len 1, val eh
11[CSM] Write on port 221h, len 1, val 44h
12[CSM] Read on port 221h, len 1
13[CSM] Write on port 220h, len 1, val eh
14[CSM] Read on port 221h, len 1
15[CSM] Write on port 220h, len 1, val eh
16[CSM] Write on port 221h, len 1, val 66h
17[CSM] Read on port 221h, len 1
18[CSM] Write on port 220h, len 1, val eh
19[CSM] Read on port 221h, len 1
20[CSM] Write on port 220h, len 1, val eh
21[CSM] Write on port 221h, len 1, val 0h
22[CSM] Read on port 221h, len 1
23[CSM] Write on port 223h, len 1, val 0h
24[CSM] Write on port 220h, len 1, val dh
25[CSM] Read on port 221h, len 1
26[CSM] Write on port 220h, len 1, val dh
27[CSM] Write on port 221h, len 1, val a0h
28[CSM] Read on port 221h, len 1
29[CSM] Write on port 220h, len 1, val eh
30[CSM] Write on port 221h, len 1, val 0h
31[CSM] Read on port 221h, len 1
32[CSM] Write on port 220h, len 1, val fh
33[CSM] Write on port 221h, len 1, val e0h
34[CSM] Read on port 221h, len 1
35[CSM] Write on port 220h, len 1, val 7h
36[CSM] Write on port 221h, len 1, val ffh
37[CSM] Read on port 221h, len 1
38[CSM] Write on port 220h, len 1, val eh
39[CSM] Write on port 221h, len 1, val 0h
40[CSM] Read on port 221h, len 1
41[CSM] Write on port 220h, len 1, val 0h
42[CSM] Write on port 221h, len 1, val 0h
43[CSM] Read on port 221h, len 1
44[CSM] Write on port 220h, len 1, val 1h
45[CSM] Write on port 221h, len 1, val 0h
46[CSM] Read on port 221h, len 1
47[CSM] Write on port 220h, len 1, val 2h
48[CSM] Write on port 221h, len 1, val 0h
49[CSM] Read on port 221h, len 1
50[CSM] Write on port 220h, len 1, val 3h
51[CSM] Write on port 221h, len 1, val 0h
52[CSM] Read on port 221h, len 1
53[CSM] Write on port 220h, len 1, val 4h
54[CSM] Write on port 221h, len 1, val 0h
55[CSM] Read on port 221h, len 1
56[CSM] Write on port 220h, len 1, val 5h
57[CSM] Write on port 221h, len 1, val 0h
58[CSM] Read on port 221h, len 1
59[CSM] Write on port 220h, len 1, val 6h
60[CSM] Write on port 221h, len 1, val 0h

61[CSM] Read on port 221h, len 1
62[CSM] Write on port 220h, len 1, val 7h
63[CSM] Write on port 221h, len 1, val 0h
64[CSM] Read on port 221h, len 1
65[CSM] Write on port 220h, len 1, val 8h
66[CSM] Write on port 221h, len 1, val 0h
67[CSM] Read on port 221h, len 1
68[CSM] Write on port 220h, len 1, val 9h
69[CSM] Write on port 221h, len 1, val 0h
70[CSM] Read on port 221h, len 1
71[CSM] Write on port 220h, len 1, val ah
72[CSM] Write on port 221h, len 1, val 0h
73[CSM] Read on port 221h, len 1
74[CSM] Write on port 220h, len 1, val bh
75[CSM] Write on port 221h, len 1, val 0h
76[CSM] Read on port 221h, len 1
77[CSM] Write on port 220h, len 1, val ch
78[CSM] Write on port 221h, len 1, val 0h
79[CSM] Read on port 221h, len 1
80[CSM] Write on port 220h, len 1, val dh
81[CSM] Write on port 221h, len 1, val 0h
82[CSM] Read on port 221h, len 1
83[CSM] Write on port 220h, len 1, val dh
84[CSM] Read on port 221h, len 1
85[CSM] Write on port 220h, len 1, val dh
86[CSM] Write on port 221h, len 1, val b0h
87[CSM] Read on port 221h, len 1
88[CSM] Write on port 220h, len 1, val 0h
89[CSM] Write on port 221h, len 1, val 0h
90[CSM] Read on port 221h, len 1
91[CSM] Write on port 220h, len 1, val 1h
92[CSM] Write on port 221h, len 1, val 0h
93[CSM] Read on port 221h, len 1
94[CSM] Write on port 220h, len 1, val 2h
95[CSM] Write on port 221h, len 1, val 0h
96[CSM] Read on port 221h, len 1
97[CSM] Write on port 220h, len 1, val 3h
98[CSM] Write on port 221h, len 1, val 0h
99[CSM] Read on port 221h, len 1
100[CSM] Write on port 220h, len 1, val 4h
101[CSM] Write on port 221h, len 1, val 0h
102[CSM] Read on port 221h, len 1
103[CSM] Write on port 220h, len 1, val 5h
104[CSM] Write on port 221h, len 1, val 0h
105[CSM] Read on port 221h, len 1
106[CSM] Write on port 220h, len 1, val 6h
107[CSM] Write on port 221h, len 1, val 0h
108[CSM] Read on port 221h, len 1
109[CSM] Write on port 220h, len 1, val 7h
110[CSM] Write on port 221h, len 1, val 0h
111[CSM] Read on port 221h, len 1
112[CSM] Write on port 220h, len 1, val 8h
113[CSM] Write on port 221h, len 1, val 0h
114[CSM] Read on port 221h, len 1
115[CSM] Write on port 220h, len 1, val 9h
116[CSM] Write on port 221h, len 1, val 0h
117[CSM] Read on port 221h, len 1
118[CSM] Write on port 220h, len 1, val ah
119[CSM] Write on port 221h, len 1, val 0h
120[CSM] Read on port 221h, len 1
121[CSM] Write on port 220h, len 1, val fh
122[CSM] Write on port 221h, len 1, val 0h
123[CSM] Read on port 221h, len 1
124[CSM] Write on port 220h, len 1, val dh
125[CSM] Read on port 221h, len 1
126[CSM] Write on port 220h, len 1, val dh
127[CSM] Write on port 221h, len 1, val 0h
128[CSM] Read on port 221h, len 1
129[CSM] Write on port 220h, len 1, val 7h
130[CSM] Write on port 221h, len 1, val ffh
131[CSM] Read on port 221h, len 1
132[CSM] Write on port 220h, len 1, val dh
133[CSM] Read on port 221h, len 1
134[CSM] Write on port 220h, len 1, val dh
135[CSM] Write on port 221h, len 1, val a0h
136[CSM] Read on port 221h, len 1
137[CSM] Write on port 223h, len 1, val 0h
138[CSM] Write on port 220h, len 1, val dh
139[CSM] Read on port 221h, len 1
140[CSM] Write on port 220h, len 1, val dh
141[CSM] Write on port 221h, len 1, val a0h
142[CSM] Read on port 221h, len 1
143...

1[CSM] Write on port 221h, len 1, val 0h
2[CSM] Write on port 220h, len 1, val 0h
3[CSM] Write on port 221h, len 1, val 1h
4[CSM] Write on port 220h, len 1, val 0h
5[CSM] Write on port 221h, len 1, val 2h
6[CSM] Write on port 220h, len 1, val 0h
7[CSM] Write on port 221h, len 1, val 3h
8[CSM] Write on port 220h, len 1, val 0h
9[CSM] Write on port 221h, len 1, val 4h
10[CSM] Write on port 220h, len 1, val 0h
11[CSM] Write on port 221h, len 1, val 5h
12[CSM] Write on port 220h, len 1, val 0h
13[CSM] Write on port 221h, len 1, val 6h
14[CSM] Write on port 220h, len 1, val 0h
15[CSM] Write on port 221h, len 1, val 7h
16[CSM] Write on port 220h, len 1, val 0h
17[CSM] Write on port 221h, len 1, val 8h
18[CSM] Write on port 220h, len 1, val 0h
19[CSM] Write on port 221h, len 1, val 9h
20[CSM] Write on port 220h, len 1, val 0h
21[CSM] Write on port 221h, len 1, val ah
22[CSM] Write on port 220h, len 1, val 0h
23[CSM] Write on port 221h, len 1, val bh
24[CSM] Write on port 220h, len 1, val 0h
25[CSM] Write on port 221h, len 1, val ch
26[CSM] Write on port 220h, len 1, val 0h
27[CSM] Write on port 221h, len 1, val dh
28[CSM] Write on port 220h, len 1, val 0h
29[CSM] Write on port 221h, len 1, val eh
30[CSM] Write on port 220h, len 1, val 0h
31[CSM] Write on port 221h, len 1, val fh
32[CSM] Write on port 220h, len 1, val 0h
33[CSM] Write on port 221h, len 1, val 10h
34[CSM] Write on port 220h, len 1, val 0h
35[CSM] Write on port 221h, len 1, val 11h
36[CSM] Write on port 220h, len 1, val 0h
37[CSM] Write on port 221h, len 1, val 12h
38[CSM] Write on port 220h, len 1, val 0h
39[CSM] Write on port 221h, len 1, val 13h
40[CSM] Write on port 220h, len 1, val 0h
41[CSM] Write on port 221h, len 1, val 14h
42[CSM] Write on port 220h, len 1, val 0h
43[CSM] Write on port 221h, len 1, val 15h
44[CSM] Write on port 220h, len 1, val 0h
45[CSM] Write on port 221h, len 1, val 16h
46[CSM] Write on port 220h, len 1, val 0h
47[CSM] Write on port 221h, len 1, val 17h
48[CSM] Write on port 220h, len 1, val 0h
49[CSM] Write on port 221h, len 1, val 18h
50[CSM] Write on port 220h, len 1, val 0h
51[CSM] Write on port 221h, len 1, val 19h
52[CSM] Write on port 220h, len 1, val 0h
53[CSM] Write on port 221h, len 1, val 1ah
54[CSM] Write on port 220h, len 1, val 0h
55[CSM] Write on port 221h, len 1, val 1bh
56[CSM] Write on port 220h, len 1, val 0h
57[CSM] Write on port 221h, len 1, val 1ch
58[CSM] Write on port 220h, len 1, val 0h
59[CSM] Write on port 221h, len 1, val 1dh
60[CSM] Write on port 220h, len 1, val 0h

61[CSM] Write on port 221h, len 1, val 1eh
62[CSM] Write on port 220h, len 1, val 0h
63[CSM] Write on port 221h, len 1, val 1fh
64[CSM] Write on port 220h, len 1, val 0h
65[CSM] Write on port 221h, len 1, val 1ch
66[CSM] Write on port 220h, len 1, val 2h
67[CSM] Write on port 221h, len 1, val 1ch
68[CSM] Write on port 220h, len 1, val 1h
69[CSM] Write on port 223h, len 1, val 0h
70[CSM] Write on port 222h, len 1, val 0h
71[CSM] Write on port 223h, len 1, val 1h
72[CSM] Write on port 222h, len 1, val 0h
73[CSM] Write on port 223h, len 1, val 2h
74[CSM] Write on port 222h, len 1, val 0h
75[CSM] Write on port 223h, len 1, val 3h
76[CSM] Write on port 222h, len 1, val 0h
77[CSM] Write on port 223h, len 1, val 4h
78[CSM] Write on port 222h, len 1, val 0h
79[CSM] Write on port 223h, len 1, val 5h
80[CSM] Write on port 222h, len 1, val 0h
81[CSM] Write on port 223h, len 1, val 6h
82[CSM] Write on port 222h, len 1, val 0h
83[CSM] Write on port 223h, len 1, val 7h
84[CSM] Write on port 222h, len 1, val 0h
85[CSM] Write on port 223h, len 1, val 8h
86[CSM] Write on port 222h, len 1, val 0h
87[CSM] Write on port 223h, len 1, val 9h
88[CSM] Write on port 222h, len 1, val 0h
89[CSM] Write on port 223h, len 1, val ah
90[CSM] Write on port 222h, len 1, val 0h
91[CSM] Write on port 223h, len 1, val bh
92[CSM] Write on port 222h, len 1, val 0h
93[CSM] Write on port 223h, len 1, val ch
94[CSM] Write on port 222h, len 1, val 0h
95[CSM] Write on port 223h, len 1, val dh
96[CSM] Write on port 222h, len 1, val 0h
97[CSM] Write on port 223h, len 1, val eh
98[CSM] Write on port 222h, len 1, val 0h
99[CSM] Write on port 223h, len 1, val fh
100[CSM] Write on port 222h, len 1, val 0h
101[CSM] Write on port 223h, len 1, val 10h
102[CSM] Write on port 222h, len 1, val 0h
103[CSM] Write on port 223h, len 1, val 11h
104[CSM] Write on port 222h, len 1, val 0h
105[CSM] Write on port 223h, len 1, val 12h
106[CSM] Write on port 222h, len 1, val 0h
107[CSM] Write on port 223h, len 1, val 13h
108[CSM] Write on port 222h, len 1, val 0h
109[CSM] Write on port 223h, len 1, val 14h
110[CSM] Write on port 222h, len 1, val 0h
111[CSM] Write on port 223h, len 1, val 15h
112[CSM] Write on port 222h, len 1, val 0h
113[CSM] Write on port 223h, len 1, val 16h
114[CSM] Write on port 222h, len 1, val 0h
115[CSM] Write on port 223h, len 1, val 17h
116[CSM] Write on port 222h, len 1, val 0h
117[CSM] Write on port 223h, len 1, val 18h
118[CSM] Write on port 222h, len 1, val 0h
119[CSM] Write on port 223h, len 1, val 19h
120[CSM] Write on port 222h, len 1, val 0h
121[CSM] Write on port 223h, len 1, val 1ah
122[CSM] Write on port 222h, len 1, val 0h
123[CSM] Write on port 223h, len 1, val 1bh
124[CSM] Write on port 222h, len 1, val 0h
125[CSM] Write on port 223h, len 1, val 1ch
126[CSM] Write on port 222h, len 1, val 0h
127[CSM] Write on port 223h, len 1, val 1dh
128[CSM] Write on port 222h, len 1, val 0h
129[CSM] Write on port 223h, len 1, val 1eh
130[CSM] Write on port 222h, len 1, val 0h
131[CSM] Write on port 223h, len 1, val 1fh
132[CSM] Write on port 222h, len 1, val 0h
133[CSM] Write on port 223h, len 1, val 1ch
134[CSM] Write on port 222h, len 1, val 2h
135[CSM] Write on port 223h, len 1, val 1ch
136[CSM] Write on port 222h, len 1, val 1h
137[CSM] Write on port 221h, len 1, val 0h
138[CSM] Write on port 220h, len 1, val 0h
139[CSM] Write on port 221h, len 1, val 1h
140[CSM] Write on port 220h, len 1, val 0h
141[CSM] Write on port 221h, len 1, val 2h
142[CSM] Write on port 220h, len 1, val 0h
143[CSM] Write on port 221h, len 1, val 3h
144[CSM] Write on port 220h, len 1, val 0h
145[CSM] Write on port 221h, len 1, val 4h
146[CSM] Write on port 220h, len 1, val 0h
147[CSM] Write on port 221h, len 1, val 5h
148[CSM] Write on port 220h, len 1, val 0h
149[CSM] Write on port 221h, len 1, val 6h
150[CSM] Write on port 220h, len 1, val 0h
151[CSM] Write on port 221h, len 1, val 7h
152[CSM] Write on port 220h, len 1, val 0h
153[CSM] Write on port 221h, len 1, val 8h
154[CSM] Write on port 220h, len 1, val 0h
155[CSM] Write on port 221h, len 1, val 9h
156[CSM] Write on port 220h, len 1, val 0h
157[CSM] Write on port 221h, len 1, val ah
158[CSM] Write on port 220h, len 1, val 0h
159[CSM] Write on port 221h, len 1, val bh
160[CSM] Write on port 220h, len 1, val 0h
161[CSM] Write on port 221h, len 1, val ch
162[CSM] Write on port 220h, len 1, val 0h
163[CSM] Write on port 221h, len 1, val dh
164...

There is some very interesting stuff. 😎

A little pause for clarification. 😲
There are four devices on the board that are connected to ISA data bus:
- AY chip
- 2x74HC365 (joystick ports)
- 74HC373 (PCM DAC)
Nothing else has access to it, even GAL does not.

Address bus pre-decoding is done by 74HC138 then GAL takes over and does all the rest of address decoding and also it knows type of access (read or write). After address decoding GAL has control over every device on the board:
- 2 pins to control AY via BDIR and BC1 (setting mode of operation: offline, write register address, write data to a register, read data from a register);
- 2 pins control each of the 74HC365s (those can only dump data to the ISA bus by read command, neither AY or GAL can read joystick ports or know about state change);
- 1 pin to control 74HC373 (it can not be read, only writes from ISA data bus are possible);
- 2 pins to control 74HC74 that after some mess outputs IRQ to the ISA.

Back to the logs.
First of all, there is frequent access to ports 0x220 and 0x221. 0x220 is the base address, so offsets +0x00 and +0x01 are frequently used.
+0x00 is always being written, never read.
+0x01 is being read or written

Reminds of anything?

If we'll look one step forward, we'll se that four MSBs in write operations to +0x00 are almost always "0".

Yep, seems like write-only operations at +0x00 are writing AY address number with BDIR="1", BC1="1".
For now let's assume that +0x01 handles data writes and reads for AY with corresponding BDIR and BC1 produced by GAL.

Let's try to "disassemble" this log:

1Example:
2// [AY] Select register D (envelope shape)
3[CSM] Write on port 220h, len 1, val dh
4
5// [AY] Read envelope shape (didn't find the default state of the register yet)
6[CSM] Read on port 221h, len 1
7
8// [AY] Repeat of register D selection (it's not necessary, address stays the same, probably just a way that procedure accessing AY in software works)
9[CSM] Write on port 220h, len 1, val dh
10
11// [AY] Write 0xAD: "D" - select rising and holding amplitude.
12[CSM] Write on port 221h, len 1, val adh
13
14// [AY] Read from the same register (for verification).
15[CSM] Read on port 221h, len 1
16
17// [AY] Select register E (data for I/O port A, which has two 4-bit DACs connected, that contol analog amplifier).
18[CSM] Write on port 220h, len 1, val eh
19
20// [AY] Write 0x00: clear both DACs.
21[CSM] Write on port 221h, len 1, val 0h
22
23// [AY] Read from the same register (for verification).
24[CSM] Read on port 221h, len 1
25
26// [AY] Select register F (data for I/O port B, that controls enabling IRQ/DRQ and switching to mono).
27[CSM] Write on port 220h, len 1, val fh
28
29// [AY] Write 0xE0: mono is disabled, IRQ is disabled, DRQ is disabled, "1" on pin 6 of the GAL.
30[CSM] Write on port 221h, len 1, val e0h
31
32// [AY] Read from the same register (for verification).
33[CSM] Read on port 221h, len 1
34
35// [AY] Select register 7 (I/O ports and mixer settings).
36[CSM] Write on port 220h, len 1, val 7h
37
38// [AY] Write 0xFF: set I/O port A and I/O port B as outputs, turn off sound for all channels.
39[CSM] Write on port 221h, len 1, val ffh
40
41// [AY] Read from the same register (for verification).
42[CSM] Read on port 221h, len 1
43
44// [AY] Repeat clearing two 4-bit DACs.
45[CSM] Write on port 220h, len 1, val eh
46[CSM] Write on port 221h, len 1, val 0h
47[CSM] Read on port 221h, len 1
48
49// [AY] Clear registers 0...D: reset all frequencies and levels, set decaying envelope, enable output of tone and noise on all channels, set I/O port A and I/O port B as inputs.
50[CSM] Write on port 220h, len 1, val 0h
51[CSM] Write on port 221h, len 1, val 0h
52[CSM] Read on port 221h, len 1
53[CSM] Write on port 220h, len 1, val 1h
54[CSM] Write on port 221h, len 1, val 0h
55[CSM] Read on port 221h, len 1
56...
57[CSM] Write on port 220h, len 1, val dh
58[CSM] Write on port 221h, len 1, val 0h
59[CSM] Read on port 221h, len 1
60[CSM] Write on port 220h, len 1, val dh

61[CSM] Read on port 221h, len 1
62
63// [AY] Set rising and holding envelope.
64[CSM] Write on port 220h, len 1, val dh
65[CSM] Write on port 221h, len 1, val bdh
66[CSM] Read on port 221h, len 1
67
68// [AY] Repeat clear of registers 0...D.
69[CSM] Write on port 220h, len 1, val 0h
70[CSM] Write on port 221h, len 1, val 0h
71[CSM] Read on port 221h, len 1
72...
73[CSM] Write on port 220h, len 1, val fh
74[CSM] Write on port 221h, len 1, val 0h
75[CSM] Read on port 221h, len 1
76[CSM] Write on port 220h, len 1, val dh
77[CSM] Read on port 221h, len 1
78
79// [AY] Set rising and holding envelope.
80[CSM] Write on port 220h, len 1, val dh
81[CSM] Write on port 221h, len 1, val dh
82[CSM] Read on port 221h, len 1
83
84// [AY] Set I/O port A and I/O port B as outputs, turn off sound for all channels.
85[CSM] Write on port 220h, len 1, val 7h
86[CSM] Write on port 221h, len 1, val ffh
87[CSM] Read on port 221h, len 1
88
89// [AY] Read (verification?) envelope shape.
90[CSM] Write on port 220h, len 1, val dh
91[CSM] Read on port 221h, len 1
92
93// [AY] Repeat setting rising and holding envelope.
94[CSM] Write on port 220h, len 1, val dh
95[CSM] Write on port 221h, len 1, val adh
96[CSM] Read on port 221h, len 1
97
98// [AY] Output value 0x0A (170) on each of 4-bit DACs: set 66% from maximum level.
99[CSM] Write on port 220h, len 1, val eh
100[CSM] Write on port 221h, len 1, val aah
101[CSM] Read on port 221h, len 1

Next in the same log there is something else interesting:

1...
2[CSM] Write on port 222h, len 1, val 90h
3[CSM] Write on port 222h, len 1, val 84h
4[CSM] Write on port 222h, len 1, val 7eh
5[CSM] Write on port 222h, len 1, val 80h
6[CSM] Write on port 222h, len 1, val 82h
7[CSM] Write on port 222h, len 1, val 82h
8[CSM] Write on port 222h, len 1, val 7ah
9[CSM] Write on port 222h, len 1, val 7eh
10[CSM] Write on port 222h, len 1, val 78h
11[CSM] Write on port 222h, len 1, val 76h
12[CSM] Write on port 222h, len 1, val 70h
13[CSM] Write on port 222h, len 1, val 86h
14[CSM] Write on port 222h, len 1, val 74h
15[CSM] Write on port 222h, len 1, val 80h
16[CSM] Write on port 222h, len 1, val 78h
17[CSM] Write on port 222h, len 1, val 74h
18[CSM] Write on port 222h, len 1, val 90h
19[CSM] Write on port 222h, len 1, val 8eh
20[CSM] Write on port 222h, len 1, val 7ah
21[CSM] Write on port 222h, len 1, val 8ah
22[CSM] Write on port 222h, len 1, val 6eh
23[CSM] Write on port 222h, len 1, val 88h
24[CSM] Write on port 222h, len 1, val 94h
25[CSM] Write on port 222h, len 1, val 80h
26[CSM] Write on port 222h, len 1, val 7eh
27[CSM] Write on port 222h, len 1, val 7ch
28[CSM] Write on port 222h, len 1, val 7ch
29[CSM] Write on port 222h, len 1, val 70h
30[CSM] Write on port 222h, len 1, val 70h
31[CSM] Write on port 222h, len 1, val 8ah
32[CSM] Write on port 222h, len 1, val 8ah
33[CSM] Write on port 222h, len 1, val 6eh
34[CSM] Write on port 222h, len 1, val 84h
35[CSM] Write on port 222h, len 1, val 8ch
36[CSM] Write on port 222h, len 1, val 90h
37[CSM] Write on port 222h, len 1, val 9ah
38[CSM] Write on port 222h, len 1, val 74h
39[CSM] Write on port 222h, len 1, val 6ah
40[CSM] Write on port 222h, len 1, val 7ch
41[CSM] Write on port 222h, len 1, val 88h
42[CSM] Write on port 222h, len 1, val 92h
43[CSM] Write on port 222h, len 1, val 92h
44[CSM] Write on port 222h, len 1, val 82h
45[CSM] Write on port 222h, len 1, val 70h
46[CSM] Write on port 222h, len 1, val 66h
47[CSM] Write on port 222h, len 1, val 7ah
48[CSM] Write on port 222h, len 1, val 8ch
49[CSM] Write on port 222h, len 1, val 94h
50[CSM] Write on port 222h, len 1, val 82h
51[CSM] Write on port 222h, len 1, val 7eh
52...

It definitely looks like writes to PCM DAC! Only writes (DAC can not be read), no address presetting, value is oscillating near 0x80 (128) - that's exactly the half of 0...255 span, so the waveform can go equal distance positive (to 255) or negative (to 0).
So, +0x02 seems to be the offset for PCM DAC!

Strangely enough there is one more address being accessed - 0x223. And it is write access. So, that can not be any of the joystick ports.
In two logs it just sometimes is being written with "00" before accessing 0x220:

1[CSM] Write on port 223h, len 1, val 0h

But in another log it is being constantly written with increasing number, interleaving with writing "0x00" to 0x222 (presumably PCM DAC port).

1[CSM]
2... Write on port 221h, len 1, val 1ch
3[CSM] Write on port 220h, len 1, val 1h
4[CSM] Write on port 223h, len 1, val 0h
5[CSM] Write on port 222h, len 1, val 0h
6[CSM] Write on port 223h, len 1, val 1h
7[CSM] Write on port 222h, len 1, val 0h
8[CSM] Write on port 223h, len 1, val 2h
9[CSM] Write on port 222h, len 1, val 0h
10[CSM] Write on port 223h, len 1, val 3h
11[CSM] Write on port 222h, len 1, val 0h
12[CSM] Write on port 223h, len 1, val 4h
13[CSM] Write on port 222h, len 1, val 0h
14[CSM] Write on port 223h, len 1, val 5h
15[CSM] Write on port 222h, len 1, val 0h
16[CSM] Write on port 223h, len 1, val 6h
17[CSM] Write on port 222h, len 1, val 0h
18[CSM] Write on port 223h, len 1, val 7h
19[CSM] Write on port 222h, len 1, val 0h
20[CSM] Write on port 223h, len 1, val 8h
21[CSM] Write on port 222h, len 1, val 0h
22[CSM] Write on port 223h, len 1, val 9h
23[CSM] Write on port 222h, len 1, val 0h
24[CSM] Write on port 223h, len 1, val ah
25[CSM] Write on port 222h, len 1, val 0h
26[CSM] Write on port 223h, len 1, val bh
27[CSM] Write on port 222h, len 1, val 0h
28[CSM] Write on port 223h, len 1, val ch
29[CSM] Write on port 222h, len 1, val 0h
30[CSM] Write on port 223h, len 1, val dh
31[CSM] Write on port 222h, len 1, val 0h
32[CSM] Write on port 223h, len 1, val eh
33[CSM] Write on port 222h, len 1, val 0h
34[CSM] Write on port 223h, len 1, val fh
35[CSM] Write on port 222h, len 1, val 0h
36[CSM] Write on port 223h, len 1, val 10h
37...

Feels like programmer error (?), substituting pair 0x220/0x221 with 0x223/0x222... But who knows? Maybe GAL can switch its decoding functions? 😕
Either way, after 0x220, 0x221 and 0x222 writes there are no more devices left on the board to write to. So, I don't know what 0x223 is directed to. Can it be mirrored to 0x220?
Also, there is no sign of reading joystick ports, strange.

Nevertheless, I've already started to try replace GAL with standard logic.
LSB address decoder: +1x 74HC138
BDIR decoder: +1x 74HC00
BC1 decoder: +1x 74HC00, +1x 74HC32

Here is my crude schematic:

Here is how it should work:

Grey text - not allowed combinations (like, simultaneous decoding of two addresses, simultaneous access for read and write).
Blue - writing address of the register to the AY.
Red - writing data to the register of the AY.
Green - reading data from the register of the AY.

How address decoder works for now:

Addition to my post above, how SMD "GAL replacement" looks like:

And something else about data being written to AY.
Most of the times register 0x0D is written with MSBs b4...b7 set to "0" as stated in datasheet:

1...
2[CSM] Write on port 220h, len 1, val dh
3[CSM] Write on port 221h, len 1, val dh
4...
5[CSM] Write on port 220h, len 1, val dh
6[CSM] Write on port 221h, len 1, val 0h
7...

But sometimes..

1...
2[CSM] Write on port 220h, len 1, val dh
3[CSM] Write on port 221h, len 1, val adh
4...
5[CSM] Write on port 220h, len 1, val dh
6[CSM] Write on port 221h, len 1, val bdh
7...

Now take a look at this:

It is totally software dependent, but while on the original card there is exactly AY8930, some software takes advantages of "expanded mode" of AY8930 by switching banks that are not available on AY-8-8910 and YM2149. Something to be aware of. 😲

And last piece of information about CSM hardware for now, joystick ports pin mapping:

1Mapping is the same for both joystick ports.
2
3Pin 1 ("Up") = DB1
4Pin 2 ("Down") = DB0
5Pin 3 ("Left") = DB3
6Pin 4 ("Right") = DB2
7Pin 5 (MB) = DB5
8Pin 6 ("Fire"/LB) = DB4
9Pin 7 = +5V
10Pin 8 = GND
11Pin 9 (RB) = NC

Fagear wrote:

But for the "original replica" what should be done? 1) Component placement and routing: a) should be left as close to original a […]
Show full quote

But for the "original replica" what should be done?
1) Component placement and routing:
a) should be left as close to original as possible (even if it degrades output quality and looks bad);
b) can be re-done in some places to get some improvements;
c) should be fully made from scratch (as an example: Malinov's OPL2 board vs. AdLib).

2) Components on the board:
a) should stay as they were: in same packages, all through-hole;
b) should be replaced with compact SMD analogs where possible.

3) Joystick ports:
a) will be implemented as on the original;
b) will be implemented as standard 15-pin PC joystick port;
c) will be removed.

I vote for 1.b, 2.a, 3. too.

Fagear wrote:

But for the "original replica" what should be done? 1) Component placement and routing: a) should be left as close to original a […]
Show full quote

But for the "original replica" what should be done?
1) Component placement and routing:
a) should be left as close to original as possible (even if it degrades output quality and looks bad);
b) can be re-done in some places to get some improvements;
c) should be fully made from scratch (as an example: Malinov's OPL2 board vs. AdLib).

2) Components on the board:
a) should stay as they were: in same packages, all through-hole;
b) should be replaced with compact SMD analogs where possible.

3) Joystick ports:
a) will be implemented as on the original;
b) will be implemented as standard 15-pin PC joystick port;
c) will be removed.

Please give some answers like "1.a, 2.b, ...".

Here are my answers :

1.a, depends, 3.a.

1, This is supposed to be a replica, something to show others how the very rare original worked. I have no issue with basic improvements to the sound quality so long as the original "stereo" function is maintained. 2 (GAL vs. discrete) is really immaterial if the functionality can be perfected in discrete SMD logic instead of a GAL if you are offering fully assembled boards 😀 3 should be kept, the digital joysticks are part of the function and charm of the original board.

So as I understand this the I/O map as we understand it thus far for this card is :
0x220 is AY control
0x221 is AY register access
0x222 is for DAC writes
0x223 is a mystery or possible alias for 0x222

Can you access the DAC via 0x378, the parallel port data register?

Do we know which addresses allow for joystick reads?

Is the board fully decoded from 0x220-0x23F (or 22F)? Do the registers repeat themselves across that address space?

Great Hierophant wrote:

So as I understand this the I/O map as we understand it thus far for this card is : 0x220 is AY control 0x221 is AY register ac […]
Show full quote

So as I understand this the I/O map as we understand it thus far for this card is :
0x220 is AY control
0x221 is AY register access
0x222 is for DAC writes
0x223 is a mystery or possible alias for 0x222

I think, 0x223 is only for triggering something in GAL. Log with many writes in 0x223/0x222 ports may be bug or conflict due to incomplete emulation of CSM.
Joysticks access may require interrupts/DMA emulation, i was too lazy to dig it 😒 .

Great Hierophant wrote:

1, This is supposed to be a replica, something to show others how the very rare original worked. I have no issue with basic improvements to the sound quality so long as the original "stereo" function is maintained.

Well, I went for 1.c variant, but preserving looks of the original board. Original layout was a mess, as I described before.
So, I've took all the same components (except output amplifiers), fixed some errors of the original design, composed all components in a way that looks "close enough" to original and made a new layout from scratch with the same schematics.

Take a look.
Here is SSI-2001 vs. SSI-2001 replica. Board on the right is significantly smaller, it has new features (like +9 V regulator for 8580 and bypass capacitors), but it looks like the original, because it uses the same parts in roughly the same places:

Now take a look at current CSM replica project:

Is it bad in your opinion and should be done "closer" to original? Or is it "close enough". 😕

Great Hierophant wrote:

2 (GAL vs. discrete) is really immaterial if the functionality can be perfected in discrete SMD logic instead of a GAL if you are offering fully assembled boards 😀

Well, full functionality of the GAL is still unknown. Addresses for joysticks are still unknown, what does write to 0x223 do - still unknown. How DMA and IRQ are used and how operate within GAL - unknown. I've just started to "emulate" already known part of the GAL in SMD. It can not be implemented in standard logic yet.

Great Hierophant wrote:

So as I understand this the I/O map as we understand it thus far for this card is : 0x220 is AY control 0x221 is AY register ac […]
Show full quote

So as I understand this the I/O map as we understand it thus far for this card is :
0x220 is AY control
0x221 is AY register access
0x222 is for DAC writes
0x223 is a mystery or possible alias for 0x222

Yep, that's it. Where are joysticks - I don't know yet. How (and what for) to use IRQ and DMA - unknown.

Great Hierophant wrote:

Can you access the DAC via 0x378, the parallel port data register?

No way, 74HC138 decodes 0x20 addresses from base that could be 0x220/0x240/0x280/0x2C0. It can not cover 0x370.

Great Hierophant wrote:

Is the board fully decoded from 0x220-0x23F (or 22F)? Do the registers repeat themselves across that address space?

It's unknown. I have the card without GAL, so I can not test anything (yet). 74HC138 decodes up to +0x20 from base (0x220 default) and then GAL takes over for LSB address decoding.

Also, I have a corrections about your article.

the bits from the joysticks are read via the AY8930's two 8-bit parallel I/O ports

They are not. I/O ports of AY are used as outputs for 4-bit DACs, controlling IRQ/DMA and switching analog switches. Joystick are read with two 74HC365 buffers by command from GAL.

I think your current layout is "close enough", I'm definitely on board with one. I like that an AY-3-8910 or YM2149 can be used for the sound chip with only a slight reduction in game support.

I'll fix that joystick error in my article. These Covoxes become more mysterious as we learn more about them.

As far as the innovation replica goes, it's a real downer that they didn't include the innovation logo.

I don't really care much about how the layout looks, but rather have a fully functional replica, even improve it for less noise, reduced component count, PCB size, everything that can make it more affordable without sacrificing quality.

moturimi1 had sent me a *.JED file that was read from the original GAL16V8. It seems like it was not protected. But also after some analysis I've came to conclusion that either this JED file or original GAL chip is corrupted.

With help of Tronix and JED2EQN utility following results were received:

1; JED2EQN — JEDEC file to Boolean Equations disassembler (Version V063)
2; Copyright © National Semiconductor Corporation 1990-1993
3; Disassembled from cms.jed. Date: 11-25-118
4;$GALMODE MEDIUM
5
6chip cms GAL16V8
7
8i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /i11=11 o12=12 
9o13=13 f14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20 
10
11@ues 0000000000000000
12@ptd unused
13
14equations
15
16o19 = /i2 * /i1 * /i6
17    + /i2 * /i1 * /i4 * /i6 * /i7 * /f14 * /i8 * i9 * i11
18o19.oe = vcc
19o18 = /i3 * /i4 * /i7 * /f14 * i8 * /i9 * /i11
20o18.oe = gnd
21o17 = /i3 * /i4 * /i7 * /f14 * i8 * /i9 * i11
22o17.oe = gnd
23o16 = /i2 * /i4 * /i7 * /f14 * /i8 * /i9 * i11
24    + /i2 * /i3 * /i4 * /i7 * /f14 * /i8 * /i9 * /i11 * i11
25o16.oe = gnd
26o15 = /i2 * /i4 * /i7 * /f14 * /i8 * /i9 * i11
27    + /i2 * /i4 * /i7 * /f14 * /i8 * /i9 * /i11 * i11
28o15.oe = gnd
29f14 = gnd
30f14.oe = gnd
31o13 = /i2 * /i1 * i5 * /i6
32o13.oe = vcc
33o12 = /i2 * /i4 * /i7 * /f14 * /i8 * i9 * /i11
34o12.oe = gnd

Input/output configuration is exactly as I've predicted:

So, total map of pins 12...19 (that could be configured as inputs or as outputs on the GAL) is: OOIOOOOO.

Next, I've substituted signals from the real board into those equations:

1Pin 12 (74HC74 /CLR): /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x A1 x /A0 = 0
2Pin 13 (74HC74 CLK): /IOW x /ACK x TC x /IOB5 = 1
3Pin 14: feedback
4Pin 15 (BDIR): /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x A0 + /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x /A0 x A0 = 0
5Pin 16 (BC1): /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x A0 + /IOW x /IOR x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x /A0 x A0 = 0
6Pin 17 (J1EN): /IOR x /BASE_ADDR x /A4 x /A3 x A2 x /A1 x A0 = 0
7Pin 18 (J2EN): /IOR x /BASE_ADDR x /A4 x /A3 x A2 x /A1 x /A0 = 0
8Pin 19 (DACEN): /IOW x /DACK x /IOB5 + /IOW x /DACK x /BASE_ADDR x /IOB5 x /A4 x /A3 x /A2 x A1 x A0 = 1

...and there are some very strange if not erroneous lines. I've checked some of those lines via manual JED decoding by following JED specification - everything matches output of JED2EQN.

Look at Pin 15: the equation consists of two "ORed" "ANDs". The pin will became active (level = 0) if left or right part ("+" as separator) will be TRUE. Left side seems fine (for now), but at the right there is "/A0 x A0". That statement will ALWAYS be false, as well as the whole right side. 😵
The same problem is in the equation for Pin 16: right side also contains "/A0 x A0". But not only that: there is also "/IOW x /IOR" (simultaneous read and write requests)! 😐
If we look closer at Pin 15 and Pin 16 together than addresses don't match with what was discovered earlier.
By the equations Pin 15 (BDIR) AND Pin 16 (BC1) should be set to "0" when writing to BASE+0x01 or to "1" otherwise. That's total nonsence, because "00" combination means "AY is not listening". Also, according to simulator logs, AY can be accessed at least via two addresses: BASE+0x00 and BASE+0x01 and both via write and read.

Correct equations should be something like this:

1Pin 15 (BDIR): /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x A0 + /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x /A0 = 1
2Pin 16 (BC1): /IOR x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x A0 + /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x /A1 x /A0 = 1

Now Pin 19 (DACEN).
Right part of the equation will never trigger because that part contains the whole left part (/IOW x /DACK x /BASE_ADDR x /IOB5 x /A4 x /A3 x /A2 x A1 x A0). 😐
If so, that means that DAC will be refreshed ONLY via DMA, which seems not to be true, because there was information that DAC on the CSM can be updated via both DMA and direct-write. Also, simulation logs showed that there are cases when software performs direct-port write to DAC via BASE+0x02. If we look at the equation, address there is translated into BASE+0x03, which also seems wrong. 😕

I think that correct equation should be like this:

1Pin 19 (DACEN): /IOW x /DACK x /IOB5 + /IOW x /BASE_ADDR x /A4 x /A3 x /A2 x A1 x /A0 = 1

Equations determine that Pin 12 will be activated when writing to BASE+0x02. As was written above, that address should belong to DAC, so I don't think that this line is correct. I think that it should be triggered on BASE+0x03. And that will solve the mystery of those strange infrequent writes to that port in simulation.
When this signal is active, it sets output of one of the 74HC74 to "0" and that will clear IRQ (if it was allowed by AY's Port B pin 6 set to "0").

Now, what is useful in this JED (with a small grain of salt).
Pin 13 (that controls count pin of the same 74HC74) will set the IRQ (if allowed by AY), and it will do that when DMA timer will elapse (/IOW x /ACK x TC x /IOB5). Seems reasonable for typical DMA operation.

Also it seems like Joystick 1 port is BASE+0x05 and Joystick 2 port is BASE+0x04 (if those equations are not corrupted).

TL;DR
I don't think that the card will work with spare GAL16V8 that I've flashed with that JED file because of corrupted equations. But I think that those can be fixed to make it work as I've described above. 😕
Also, I think there no more "hidden secrets" in that GAL and now the replacement schematics can be done for it. 😎

I'm in the process of recreating schematics based on standard NAND and OR gates (74HC00 and 74HC32) that were already used in FMonster project (to keep the same BOM).
At the moment there are 4x 74HC00 and 2x 74HC32 for "GAL replacement".
I'm shuffling around those gates and there is no final schematic yet, but I'm working on it.

At the moment almost the whole digital part of the board is done. Analog was not touched yet and I still don't understand how to replace that LM13600...

Current "GAL replacement" looks like this:

And should work like this:

Hehe i like the irony, Proud to be made in USA -> and now "Designed in Russia" 😁

I've ordered first prototypes of CSM replica... 🙄

JLCPCB ? 😁

Tiido wrote:

JLCPCB ? 😁

JLCPCB it is! I usually use PCBWay, but for boards <100 mm. JLCPCB was the cheapest way to get >100 mm board with proper gold finish on the edge connector.

Really looking forward to this, great to finally see this project close to a conclusion. Hope the prototypes work well. I have a plethora of different DOS systems if you need testers.

If one wants this card to work alongside a SSI-2001 replica, one compromise has to be made since for cards share the 280h address as default. The list of supported games is small so patching is always a solution.

First prototypes of the replica showed up:

I've started to assemble the prototype board.

Not all of the parts are available now.

Amazing!

I bought some AY-3 chips from China couple of years ago (see start of thread) incase you have trouble sourcing it. They turned out to be the real thing according to Yvan256