The extra bit on a 32Kx9 SRAM is for parity; your 486 board might use it if all the SRAM is the same type and the BIOS supports it, or it just ignores it and merely affords flexibility.

Thanks

OK, so I bought 4 32kx8 SRAM cache chips.

I went to install them and noticed that 4 of the sockets are a little longer than the chips. 2 of the sockets appear to be the correct size.

I think I heard that my shorter chips should work in the longer slots. Is that correct?

If so, what is the correct orientation for the chips?

Also, why does the board have 4 long sockets and 2 short sockets for the cache? I assume all 6 sockets are for cache...

Please see my picture. The cache module is just sitting on the slot, it is not installed. Is this the correct orientation?

Thanks.

tegrady wrote:

I think I heard that my shorter chips should work in the longer slots. Is that correct?

Yes, it was common in those days to see shorter chips in longer sockets. Not sure why exactly, but in general it should work.
I think the extra unused pins should always be on the side of the notch.

tegrady wrote:

Also, why does the board have 4 long sockets and 2 short sockets for the cache? I assume all 6 sockets are for cache...

The cache uses regular storage for the data, and also something known as 'tag ram', which is where it basically stores the cache state. The shorter sockets are probably used as tag ram (which are just regular SRAM chips).

OK. Is the Cache in my picture aligned properly then?

Also, do you think I could just buy two more of the same cache chip and put them in the TAG Ram sockets?

Thanks.

tegrady wrote:

OK. Is the Cache in my picture aligned properly then?

Yes, seems so. Notch should be on the same side as where it's marked on the board and/or socket. And then leave two rows of pins empty. So the non-notched part of the chip should be flush with the end of the socket.

tegrady wrote:

Also, do you think I could just buy two more of the same cache chip and put them in the TAG Ram sockets?

I'm not 100% sure, but I'd say it's a reasonably safe bet (it's like that on most boards as far as I know).

So I tried it in the configuration shown above and got a "bad cache ram" error on startup... Not sure what the issue is.

Jumper settings on the mobo? Usually there are some jumpers to set according the amount of cache installed

The only jumper is to select 32kx8 vs 32kx9. I found the jumper, but it is soldered to the board and is permanently set to 32kx8, which is the type of cache I have.

I have attached the jumper settings document. Let me know if I am missing anything. Thanks.

I'm not sure which end of the socket has pin 1, but when using 28-pin SRAM in a 32-pin socket, pin 1 of the SRAM is technically supposed to occupy the position for what would be pin 3 of a 32-pin SRAM (that is to say, like Scali says, leave the 4 pin positions (#'s 1, 2, 31, 32) empty, and pins 14 & 15 of the SRAM are flush with the back end of the socket, in what would be positions #16 & 17 of that socket). So be sure you know which end of the socket has pin 1.

Looking at the jumpers, you only have the 'choice' with your SRAM select of 32Kx8; which means it's non-parity, so be sure that the parity select jumper (JP25) is set to either "disable parity check" (or, based on your DRAM, "check DRAM only"); if it's trying to check parity on the cache (which doesn't/can't support it) that could be the failure point.

I think you need 8k x8 (32k will do) in the other sockets for tag, only one might be needed for writethrough, but the dirty bit for writeback wouldn't fit in just one (unless using less than half the max RAM)

Maybe...

-post a photo of your current sram configuration
-make sure the srams are seated properly
-make sure no dud is among them(put a finger on each sram when running - a very hot one may be faulty)

You got 128K of cache which can be paired with a smaller tag ram(8K since there are only 8k cache lines), but doesn't have to be.