At least on 486s, I don't think there is much of a difference in performance by setting the L2 cache as writeback vs write through. I also remember testing a board and noting that when L2 was set the writeback the main memory speed decreased...though the overall system speed increased by a small %.
It also depends on the board and chipset design. I've heard that a well designed L2 write through cache can out perform writeback. Also, on most boards enabling write back mode will decrease your cacheable RAM area by 50%, so if you have a lot of RAM it's better to set write through.

Now L1 cache is a totally different thing. That is definitely worth enabling if the CPU motherboard and CPU support it. CPU performance advantage is about 10% I believe. Getting that going can be more problematic though. especially on boards made before 1995. I think I heard some of the boards designed to support the writeback mode of early Cyrix 486 CPUs like the 486S don't support writeback implementations of later chips like the 5x86. Also, it can cause major problems with VLB SCSI controllers.

I have noticed the same on some SIS471 motherboards, which happens to be the same chipset as yours. However, I fail to understand the reason why this happens... in some cases, if using WT L1, then WB L2 is faster, but with WB L1 (on CPUs that support it), then WT L2 is faster. Using different sticks of RAM or cache chips does not change anything, so I assume it has to do with the chipset?

The issue is with the bios.
Correct me if I am wrong but that AMD 5x86 CPU is not supported on that motherboard.
I ran into this same problem.
Play around with the timing settings and find which works best. I used Speedsys program to test the CPU and cache.
Socket-3 PCI motherboards usually support this CPU.
Also I was told the Gigabyte GA-5486-AL bios supports this CPU better.
Or maybe the Gigabyte 486vs bios. For VLB motherboard.

See this posts :
AMD 5x86@160mhz., Media Vision PAS16. ( Win 95 )

You might want to try an AMD 5x86 over drive chip by “trinity works” or “evergreen”.

See my posts:
486 Overdrive CPU's - Intel and AMD ?

Are you using a CPU interposer? I don't believe this board has configurable CPU voltage, so be aware that plugging a 5x86 in directly will supply 5V instead of the correct 3.3V (or was it 3.45V?)

I use a Trinityworks 5x86 module in this board, and it works at 133MHz with write-back L1 with the correct dipswitch settings on the module itself. If you don't have an interposer with its own jumpers/switches, it may be possible to enable these settings with the motherboard jumpers. But the settings aren't given in the documentation (there are several jumpers but their function isn't broken down in detail, and the same combinations are listed for different CPUs which one would expect to have differing settings) so it might take some experimentation to figure out how.

I have also found this board to be picky about RAM, it only works with FPM and not with EDO.

As for the reduced memory performance when L2 write-back is enabled, I just assumed it was a poor implementation in this chipset. When data is read from DRAM it is copied into the L2 which causes some old data to be displaced from the L2. The way it should work is that the displaced data is only written back to DRAM if it has actually changed. But SiS 471 must be writing ejected data back to DRAM even when it has not changed, which wastes time in between DRAM reads. But I haven't seen any authoritative documentation to say whether they designed it this way or if there is another reason for this behavior.

Just writing here so it would be easier for me to monitor the topic.

I too have a motherboard (Soyo 25P2) where Write-Back L2 shows lower memory bandwidth than Write-Through. (I have Am486DX4-100 with write-through L1)

This bios setting seem to work best for my motherboard.
AMD 5x86@160mhz., Media Vision PAS16. ( Win 95 )

Its an issue with missing Dirty tag, which is needed for successfull WB strategy. You can check the availibility with the ctcm tool. If you have no dirty tag, then you can fix it with a BIOS Update or, in case of SiS471, with Hardware Hack. The 471 in general supports dirty tag.

PC-Engineer wrote:

Its an issue with missing Dirty tag, which is needed for successfull WB strategy. You can check the availibility with the ctcm tool. If you have no dirty tag, then you can fix it with a BIOS Update or, in case of SiS471, with Hardware Hack. The 471 in general supports dirty tag.

CTCM? Creative sound blaster PNP management tool?

https://www.heise.de/download/product/ctcm-1825

PC-Engineer wrote:

Its an issue with missing Dirty tag, which is needed for successfull WB strategy. You can check the availibility with the ctcm tool. If you have no dirty tag, then you can fix it with a BIOS Update or, in case of SiS471, with Hardware Hack. The 471 in general supports dirty tag.

Interesting, what you said led me to a post by feipoa from a few years back:

Need help with FIC 486-VIP-IO and AMD 486 120mhz

It seems to have some additional information related to this issue.

OMG, thank you guys!

The board is Soyo SY-25P or 025P2, both are right. (No separate socket for dirty tag cache)
I had the same problem as described here - WT cache shows over 100MB/s memory bandwidth with speedsys, WB shows a bit over 30MB/s.

So first, the only ctcm 1.5 version worked correctly. newer ones (1.6 and 1.7) after counting something after "cacheable area" lines - 1.6 restarted and 1.7 hanged.
But the 1.5 version worked, and it did show that i have a problem with "Dirty Tag L2" (didn't exist or something)

So next to the modbin. First of all, only older modbin's work with award 4.50 bioses. i found many variants of it, that were meant for newer bioses and didn't support mine.
Next i searched out the sis 471 datasheet: ftp://retronn.de/docs/chipset/SiS%20471.pdf

In there, there is a register 72, bits 2 and 1. Both should be set to 1. For my bios, modbin showed, it was 1 and 0. I changed it to 11. Next, for good measure because of the note, i also changed register 50 bit 3 to 1.

I flashed the bios with eeprom programmer and voila! Both WT and WB show 100+MB/s memory bandwidth and ctcm shows different speeds with average "Miss + Hit", "if clean" and "if dirty" measurements. Before, with WB, all of them had equally bad values. Also it shows that "Dirty Tag L2" is "ok".

A very quick benchmark showed that pc player benchmark went from ~14.7fps (WT previously) to 15.3fps (WB now).

I love the modbin! I had amisetup tool for AMI bioses, but nothing for Award bioses to change register values or anything. Now i do!

Thank you so much for the hints! Hope it helps someone else as well. 😀
Attached the modded bios as well. It's based on 1995 J1 version of bios (latest i'm aware of). I did enable one hidden setting as well, DRAM burst write, which was enabled by default.

EDIT: Did some more benchmarking now with modded bios and between changing only to WT vs WB.
Machine itself has a Am486DX4-100 cpu, 2x32MB FPM ram, S3 805 VLB graphics.

So here's the results: (WT / WB)

3D Benchmark (fps): 64,6 / 67,3
PC Player Benchmark (fps): 14,8 / 15,3
Doom max detauls (elapsed ticks): 2099 / 1900
Topbench (score): 235 / 267
Speedsys memory bandwidth (MB/s): 113,07 / 113,06
Speedsys memory speeds in order on bottom right graph (MB/s): 73-51-43 / 73-51-38
CTCM benchmarks in order (MB/s): 65-31-31-31-31 / 65-35-26-15-13

So in general, nice boost! CTCM measurements are a bit confusing for me, but other benchmarks show a clear improvement.

Okay, thanks again and i will stop hijacking other person's thread. 😀

Wow didn't expect so many replies. Thanks guys.

Some short responses to above posts:
- The board/bios does not support the 5x86 133 but the chipset does, it's just stuck running as a DX4 in X3 which shouldn't be an issue (i don't think)
- This board has a voltage regulator and accepts DX4 CPUs natively, so I would assume I'm running at 3.3 or 3.45V, it's not user configurable but the board does mostly everything automatically to my behest (re 5V questions)

Re the dirty tag cache, that sounds very interesting. I do see the mentioned section in the manual for my chipset

If the external cache is set to write back mode ( register 50 bit 3 = "1" ) then 1 0 : no Alter bit ( always dirty ) 1 1 : combi […]
Show full quote

If the external cache is set to write back mode ( register 50 bit 3 = "1" )
then
1 0 : no Alter bit ( always dirty )
1 1 : combine 7 tag bits + 1 Alter bit in one SRAM

However, the link PC-Engineer left is taking me to a dead end. Can I bother somebody to post CTCM v.1.5 for me? My searches are, of course, only bringing up Creative's CTCM.

PC-Engineer also mentions a hardware hack to fix this, any documentation? Not sure how I'd go about flipping the bit(s). I don't have an EEPROM burner to modify the bios but could maybe outsource the job. Maybe a bios exists for this board that could bring the 5x86 to life for me as well, since I know the chipset supports it.

!!Feel free to hijack the thread Gigahertz, this is helpful information others will want a fix for at some point!! Also, which version of modbin did you use? this board also has an award 4.50G bios.

Here you go!

I tried to google any hardware solutions as well, but didn't find anything. If you do, sure share it with us. 😀

FYI, my board's default bios chip had read-only flag set (Or it was a write-once chip), so some time ago, when i wanted to upgrade the bios, i had to order new eeprom chip itself as well. The new eeprom, i can program pretty much as many times as i want. (Sure, it wears out after few thousend times...)

Modbin, i used latest one, that wasn't some kind of modbin6 or modbin version 2.xxx. Here's the link: http://www.lejabeach.com/ECS/Modbin-4.50.82a.zip

Thank you GigAHerZ! Lets see if this turns up my problem, I expect it will. Will update.

Maybe I should invest in my own burner and some blanks. I wouldn't want to write over the existing one anyway, just in case...

XMM not installed ! CTCM uses Memory from address 00120000 Int15-Memory=15728640 […]
Show full quote

XMM not installed !
CTCM uses Memory from address 00120000
Int15-Memory=15728640

CTCM, translated by Thomas Pabst, copyright ct-Mag. V1.5b/t2
Processor-Timing : i486DX,i487DX,i486DX2,am486DX,am486DX2,am486DX4,am5x86
Processor CPUID : am486DX4/ Typ:00 Fam:04 Mod:08 Stp:04
Clck : 119.8 MHz
internal Bus : 32 Bit between CPU and primary Cache or Memory
FPU : i487-Typ
L1 Cache : 16 KByte,4-way associative
L2 Cache : 256 KByte, direct mapped
Write Strategy L1 : Write Thru
Write Strategy L2 : Write Back
Dirty Tag L2 : n/a

Through Put & Bus Performance: Main Memory from 00120000

Best Time for 16K MOVSD (Cache /Page Hits) : 207 mcs - 79.2 MByte/s
average t. for 16K MOVSD (Miss + Hit) : 386 mcs - 42.4 MByte/s
average t. for 16K MOVSD (if clean) : 999 mcs - 16.4 MByte/s
average t. for 16K MOVSD (if dirty) : 999 mcs - 16.4 MByte/s
Main Memory 16K MOVSD (Cache misses) : 1131 mcs - 14.5 MByte/s

average with 256 KB L2-Cache /DOS (640K) : 522 mcs - 31.4 MByte/s
average with 256 KB L2-Cache /WIN (4M ) : 794 mcs - 20.6 MByte/s

Well, here are my results. So I get Dirty Tag L2 : n/a, is that what happened to you too Megaherz? Also wish I could get the L1 in writeback all on the VLB board.. shouldn't have sold my other UMC board that could have used the 5x86.

@BeginnerGuy, yes, i had same message for L2 dirty tag.

To get L1 into Write-Back mode, the first thing is you need to have the CPU, that has this capability. As far as i know, it's more related to hardware than configuration or software. Some later 486 CPUs have the L1 in WB, older ones have it in WT.

Thanks GigAHerZ. I'm going to see if I can dump the bios and modify it, have to get a friend to burn it for me since I don't have an EEPROM burner on hand. I'm sure that's going to be the fix.

As for L1 mode, I have an AM5x86 133MHZ ADZ model running in there, it for sure supports L1 in WB mode, it just defaults to WT and there's nothing I can do about it since the bios thinks it's a plain old Intel DX4. I know it can be done using pull down resistors (http://web.inter.nl.net/hcc/J.Steunebrink/amd5x86.htm) but I don't feel like taking it that far. I seem to have it stable at 50 bus now so I'd say at 150MHz even with write-through this is a stupid fast 486 rig.

edit: False alarm on the 50 bus, she just crashed after a while. jinxed myself there 😜

By datasheet, the L1 WriteBack enable/disable should be register 50 bit 4. Maybe you can enable it by modifying the bios on that part. 😉

GigAHerZ wrote:

By datasheet, the WriteBack enable/disable should be register 50 bit 4. Maybe you can enable it by modifying the bios on that part. 😉

Way to think ahead, that's a great Idea! Thanks 😉.. I know this chipset supports writeback so you may be on to something. Now If I can just get the bios to recognize the 5x86.. There must be some kind of microcode going on since my bios uses the same exact jumper settings for many different CPUs (DX2, DX4, POD83). According to my above link the chipset supports the AM5x86 and writeback l1 cache, just needs a proper bios.