Some lower quality boards during that era are very quirky with RAMs as mentioned by Horun. I suspect it's more to PCB design than chipsets (well, Opti is good chipset but SARC I don't know). The traces from north bridge to SIMMs needs to be in equal length so that the signals arrive at the RAM chips in sync. If not then the timing will become more critical, hence the board becomes "choosy". Biostar being a brand name might have more stringent control on the traces in terms of PCB design.

Are you able to see the RAM timing in the Biostar BIOS? If so perhaps you could copy them over to your other 2 boards and try them out.

NScaleTransitModels wrote on 2020-06-20, 02:26:

I didn't get a shot, but it looked something like this: https://www.betaarchive.com/imageupload/2015-08/1440457032.th.22699.png […]
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I didn't get a shot, but it looked something like this:

Except it was right after the "preparing setup wizard" loading bar. This time, I'm having a different problem altogether. I'm not even sure if it has to do with the memory, or my graphics card (Cirrus GD5422), or the CPU running above spec. The setup completed without any crashes or freezes, but I'm getting strange graphical glitches upon reaching the desktop. Restarted and same deal. I even tried another graphics card, a GD5429, with similar graphics issues.
graphics glitch.png

I'm starting to think this board just has a bad chipset 😕

Could be, that is definately a video glitch, could be Vid card issue or driver. Cirrus chips are generally supported under Win9x.

NScaleTransitModels wrote on 2020-06-20, 02:46:

But I'm still not entirely sure why it won't work with the 9-chip 4mb SIMMs.

Yes makes no sense. Have to take care of the better half, will try to give some better informative info tomorrow.

kalohimal wrote on 2020-06-20, 03:19:

Some lower quality boards during that era are very quirky with RAMs as mentioned by Horun. I suspect it's more to PCB design than chipsets (well, Opti is good chipset but SARC I don't know). The traces from north bridge to SIMMs needs to be in equal length so that the signals arrive at the RAM chips in sync. If not then the timing will become more critical, hence the board becomes "choosy". Biostar being a brand name might have more stringent control on the traces in terms of PCB design.

Are you able to see the RAM timing in the Biostar BIOS? If so perhaps you could copy them over to your other 2 boards and try them out.

It just could come down to PCB design if both have reputable chipsets. Interestingly enough, the Biostar has less options and completely different options under advanced chipset setup. I'm not sure how they'd translate over to the Shuttle's BIOS options. The BIOS on the Biostar:

Slow refresh cannot be disabled, only set to 15, 30, 60, and 120. CAS and RAS are "normal" or "enabled". And no DRAM waitstates option 🤔

Stable BIOS settings on the Shuttle:

Yeah then I guess your options are quite limited, perhaps can use SIMMs with faster timing. Btw when CMOS is reset, my 486 board (also a cheap brand J-Mark board with AMI BIOS) will load up the default values which are conservative. The DRAM read wait state is set to 2 and write wait state to 3.

I was able to get the PCChips board to run at 33mhz using the jumper setting. No idea why it wouldn't work at 33 last time. However, as expected, it didn't fix the video glitch issue in Win95.

I'm starting to think the cheapass SARC chipset just doesn't like Cirrus video cards 😂 I swapped in the ATI Mach8 from the Biostar system and now the PCChips is fine. I wasn't able to duplicate the glitches I'd gotten on the Cirrus GD5422 and GD5429.

Ironically enough, the Biostar doesn't like the ATI at all (screen flickering). But then again, that board sadly has serious corrosion damage 😕

kalohimal wrote on 2020-06-20, 06:30:

Yeah then I guess your options are quite limited, perhaps can use SIMMs with faster timing. Btw when CMOS is reset, my 486 board (also a cheap brand J-Mark board with AMI BIOS) will load up the default values which are conservative. The DRAM read wait state is set to 2 and write wait state to 3.

IMG_20200620_142709a.jpg

Yeah my next step is to try 60ns 9-chip SIMMs once I receive them. Strange how my Shuttle board defaults to the tightest timings instead... and HDD type 17 (why 17 in particular 🤔) but I guess that's just how it is.

NScaleTransitModels wrote on 2020-06-20, 05:49:

Slow refresh cannot be disabled, only set to 15, 30, 60, and 120.

One of these all-to-often confusing setup option names. "15" is the settings you would call "disabled".

The setting actually seems to mean "refresh interval in microseconds". Industry standard is 15.6 microseconds per row, which yields 2 milliseconds per all 128 rows of a chip with 128 rows and columns (16 kilo-entries). This matches the usual requirement given in https://console5.com/techwiki/images/8/85/MK4116.pdf, see page 3, 4th to last entry in the table. Later chips are usually designed to be compatible with that, see for example http://pdf.datasheetcatalog.com/datasheet/sie … 117400BT-50.pdf (a typical 4Mx4 chip you would find on a 3-chip 4 Meg module). "It says 2048 refresh cycles, 32ms" on the front page. So it needs an 11-bit row number (can count from zero to 2047) on RAS-only refresh, and it includes an internal 11-bit row counter form CAS-before-RAS refresh. If you divide 32 milliseconds (per chip) by the number of refresh cycles needed to refresh the whole chip, you get 15.6 microseconds. This is why you need to choose 15. Higher numbers mean less refresh cycles, and thus slightly increased performance at the risk of memory corruption. You can safely use slow refresh if you have special memory chips for low-power application applications that are designed for being refreshed less often. Typical PC SIMMs do not have these special chips.

See https://www.datasheets360.com/pdf/-5753780607200078319 for a datasheet that includes a low-power version with an extended refresh period of 128ms per chip instead of 16 ms per chip (at 1024 cycles per chip). If all memory modules in your computer had low-power chips like the -S model in that datasheet, you can safely use the setting 120.

Shuttle: replace the caps with decent low-ESR electrolytics. PCChips: what brand/series are your replacement caps? If not a reputable brand/good series: replace them too.

mkarcher wrote on 2020-06-20, 08:22:

See https://www.datasheets360.com/pdf/-5753780607200078319 for a datasheet that includes a low-power version with an extended refresh period of 128ms per chip instead of 16 ms per chip (at 1024 cycles per chip). If all memory modules in your computer had low-power chips like the -S model in that datasheet, you can safely use the setting 120.

That gets me wondering how common those low-power SIMMs are, seeing as how most BIOSes of the time seem to support them. Doing a quick search on Ebay, I wasn't able to find any modules that were marked with a -6S, -7S etc. or any specified for low power. I did come across some on Amazon that mentioned low power consumption in the description, but even these don't have a -6S or any special markings: https://www.amazon.com/MEMORY-macintosh-Music … r/dp/B017YEI5TC

evasive wrote on 2020-06-20, 11:04:

Shuttle: replace the caps with decent low-ESR electrolytics. PCChips: what brand/series are your replacement caps? If not a reputable brand/good series: replace them too.

I thought that tantalums were more reliable than electrolytics on old hardware, as long as they're powered up every now and then? These are the two kinds I see on the Shuttle, and none of them seem damaged:

The first looks like a 10μF, 16V but not sure about the second one. Also I don't have access to a soldering iron at the moment, so the caps on the PCChips are still original. Uranus branded, 10μF 25V?

The 9 chip simms did you enable parity on the motherboard?

Opti and Sarc (pcchips) are not the greatest chipsets. I had best success with SiS mostly, but not yet on VLSI or VIA.

Cheers,

pentiumspeed wrote on 2020-06-20, 23:47:

The 9 chip simms did you enable parity on the motherboard?

Opti and Sarc (pcchips) are not the greatest chipsets. I had best success with SiS mostly, but not yet on VLSI or VIA.

Cheers,

You can enable parity with 9 chip but is not required to be enabled if your board supports non-parity simms. Most XT and 286 required parity but it was slowly dropped during 386/486 era for desktop computers.

pentiumspeed wrote on 2020-06-20, 23:47:

The 9 chip simms did you enable parity on the motherboard?

Opti and Sarc (pcchips) are not the greatest chipsets. I had best success with SiS mostly, but not yet on VLSI or VIA.

Cheers,

There are no options, BIOS or jumpers, for parity or anything that could be related on either board. The PCChips actually has a build date of 02/1994 on the sticker; I would've expected it to support non-parity (and have the option). But yeah, I believe my 9-chip's are parity and should still work in theory.

SiS motherboards seem pretty rare for 386's. Not sure if I've seen any recently. Do you know if UMC or "Chips" (not PCChips) are any good? They seem to be the most common, after Opti.

Horun wrote on 2020-06-21, 00:48:

Most XT and 286 required parity but it was slowly dropped during 386/486 era for desktop computers.

It seems most 386 boards still require parity. I was not able to get non-parity modules to boot in any of my 386 systems and I didn't see a parity option. My Dell 486P/50 (early 486 from 1992) also requires parity.

Also, speaking of chipsets (hope it's not too off topic): are there any known to be good for a 50mhz overclock via 100mhz oscillator? In particular, I'm looking at getting another board for this purpose with Opti 82C392 (like my Shuttle board), but stamped for 40mhz.

NScaleTransitModels wrote on 2020-06-21, 03:11:

There are no options, BIOS or jumpers, for parity or anything that could be related on either board. The PCChips actually has a […]
Show full quote

pentiumspeed wrote on 2020-06-20, 23:47:

The 9 chip simms did you enable parity on the motherboard?

Opti and Sarc (pcchips) are not the greatest chipsets. I had best success with SiS mostly, but not yet on VLSI or VIA.

Cheers,

There are no options, BIOS or jumpers, for parity or anything that could be related on either board. The PCChips actually has a build date of 02/1994 on the sticker; I would've expected it to support non-parity (and have the option). But yeah, I believe my 9-chip's are parity and should still work in theory.

SiS motherboards seem pretty rare for 386's. Not sure if I've seen any recently. Do you know if UMC or "Chips" (not PCChips) are any good? They seem to be the most common, after Opti.

Horun wrote on 2020-06-21, 00:48:

Most XT and 286 required parity but it was slowly dropped during 386/486 era for desktop computers.

It seems most 386 boards still require parity. I was not able to get non-parity modules to boot in any of my 386 systems and I didn't see a parity option. My Dell 486P/50 (early 486 from 1992) also requires parity.

Also, speaking of chipsets (hope it's not too off topic): are there any known to be good for a 50mhz overclock via 100mhz oscillator? In particular, I'm looking at getting another board for this purpose with Opti 82C392 (like my Shuttle board), but stamped for 40mhz.

If memory serves, there were SIMMs with fake parity logic that never found errors, but simply generated the expected checksum from the actual data bits .

EDIT: Found a reference to those . http://bat8.inria.fr/~lang/hotlist/hardware/s … ver/parity.html

NScaleTransitModels wrote on 2020-06-20, 22:33:

I thought that tantalums were more reliable than electrolytics on old hardware, as long as they're powered up every now and then […]
Show full quote

I thought that tantalums were more reliable than electrolytics on old hardware, as long as they're powered up every now and then? These are the two kinds I see on the Shuttle, and none of them seem damaged:
shuttle 20200620_151033.jpg
shuttle 20200620_150954.jpg
The first looks like a 10μF, 16V but not sure about the second one.

I have already seen quite a few cases where they will simply transform into a little cloud of smoke. Powered on every now and then or not.

NScaleTransitModels wrote on 2020-06-20, 22:33:

Also I don't have access to a soldering iron at the moment, so the caps on the PCChips are still original. Uranus branded, 10μF 25V?
pcchips 20200620_145902.jpg

The only "Uranus" brand I can find is from India. But by the looks of the thing it was stripped from a portable radio somewhere in the last century. Replace them all please.

mkarcher wrote on 2020-06-19, 10:38:

There is one important difference between 1MB and 4MB modules though, and that is refresh. Every *row* of the module needs to be refreshed often enough, and the classic RAM requires the mainboard to tell the row number to the RAM chip. 4MB modules have twice as many rows as 1MB modules (in general), so the number of the row to be refreshed needs to have an extra bit. If the mainboard does not provide enough row number bits for refresh, your symptoms are explainable. There is something to the rescue, though. "Modern" RAM chips (and all 4MB SIMM chips are modern in that regard) have their own built-in refresh row counter, and if you don't use the classic refresh protocol ("RAS-only refresh"), but the newer one ("CAS before RAS refresh"), refresh works independent of the mainboard. If you happen to have an option like "CAS-before-RAS refresh" or "hidden refresh" in the BIOS setup, try enabling it...

Hi, as I tested more 386 MBs I find that 4MB modules are quite often unrealiable/unusable on many of them.
Does someone put some effort to make a MB/chipset compatability list with modern 4MB modules?
I just repaired one MB with Macronix MX83C305/306 (my thread: 386 MB chipset Macronix MX83C305/306 schematic reverse engineering and repair) and found it's unusable with 4MB modules with any SETUP settings, even I tried both original AMI BIOS and with MR BIOS for Octek Jaguar V.
I focused a bit on the refresh you told...
In datasheet I can see that 4Mx4 DRAMs usually have 2 048-Cycle Refresh in 32 ms for TMS417400A
So I tried to watch A10 an A9 lines on SIMM socket. I put CPU in HLT so it wouldn't be disturbed by memory access from BIOS/DOS.
Then I can clearly see 15us pulses. One setting matters - hidden refresh. If enabled, then A10 goes to 0 all the time and refresh pulses are only at A9. When disabled, there are pulses at both pins. So I though I got it but even when I disabled hidden refresh it still crashes with 4MB modules (memtest, w95, almost any pmode app starts...)
So I gave up on this MB, put 8 x 1MB modules in and everything runs stable, so it seems this chipset is no-go with 4MB modules. But the MB manual mentioned it could be populated with 4MB modules up to 32MB...
Then I tried one more 386DX MB Abit with Chips 82F351/355 and it also behaves very nasty. It even caused generating NMI even if parity checks was disabled in SETUP and Memtest caused always immediate reset so another no-go chipset. So it seem only my KMC-A419-8 with Ali M1419 chipset can work with 4MB modules. It also sometimes thow some error in Memtest but in GoldMemory not and also PM apps and W95 runs stable. So it seems to me that only late 386 and 486 chipsets can work with them...

RayeR wrote on Yesterday, 17:14:

I focused a bit on the refresh you told...
In datasheet I can see that 4Mx4 DRAMs usually have 2 048-Cycle Refresh in 32 ms for TMS417400A
So I tried to watch A10 an A9 lines on SIMM socket. I put CPU in HLT so it wouldn't be disturbed by memory access from BIOS/DOS.

That's a good way to test the refresh pattern.

RayeR wrote on Yesterday, 17:14:

Then I can clearly see 15us pulses. One setting matters - hidden refresh. If enabled, then A10 goes to 0 all the time and refresh pulses are only at A9. When disabled, there are pulses at both pins.

With hidden refresh enabled, the address pins do no longer matter. So with hidden refresh enabled, you should be fine no matter what the board does, because hidden refresh is a variant of CBR (CAS before RAS) refresh, which can be performed in parallel with a useful memory access. The idea of hidden refresh is that on the last cycle that hits a page, you negate /RAS right after asserting /CAS. Asserting /CAS will put the final nibble of data into the output latches while negating /RAS allows you to assert /RAS again with /CAS still active, which will trigger a CBR refresh and refresh the "next row that is due" using a row counter integrated into the memory chip. You should verify whether your chipset actually does CBR refresh with hidden refresh enabled. You can scope /RAS and /CAS on your two channels, and check whether /CAS goes low first, as required for CBR.

Furthermore, if A10 pulses high on every refresh with hidden refresh disabled, this is a problem. you expect 16ms of refresh cycles with A10 being low (no pulses, if your system has A10 low while it is idle) followed by 10ms of refresh cycles with A10 being high (during the refresh cycle, so you will see pulses). If A10 is high on every refresh cycle for standard /RAS-only refresh, only the "upper half" of the RAM will be refreshed. I assume that hidden refresh disabled causes /RAS-only refresh (no pulses on /CAS at all).

I had no issues using 3-chip 4-MByte SIMMs on a TOPCAT 80386SX board, so either you are having really bad luck with the chipsets you tried, or your modules behave strange.

Regarding the NMI/parity issue: You should check whether your SIMMs are nonconformant and bridge parity in (pin 29) to parity out (pin 26). This is typically not an issue on 486 boards, as 486 processors use bidirectional parity pins and have the parity comparator integrated in the processor, whereas 386 boards might connect the output of an 9-bit parity generator permanently to "parity in", while "parity out" is gated as 9th input to the parity generator only on read cycles, in which the output of the parity generator is used as NMI signal. Feeding back the parity generator output to its input through a bridge on the SIMM during read cycles can cause invalid behaviour. Nonconformant SIMMs bridging pin 29 to 26 would be a perfect explanation why they refuse to work in mostly anything before chipsets that support 486 processors.

OK, when I'll have a time I can scope RAS, CAS signals but as it's failing regardless hidden refresh enabled / disabled I don't see any hope for that MB (If there will be no proper CBR I can't do anything with it anyway...).
Yes I also tried 2 386SX boards with 2 modules and they worked. I wonder that SX boards would be newer than DX boards...

The 4MB modules I have are homemade on PCB design by Alex G.
http://www.alexandrugroza.ro/microelectronics … simm/index.html
and now I put on parity DRAM chip GM71C4100CJ-60 http://datasheet.octopart.com/GM71C4100CJ-60- … t-180600006.pdf
that has separate DIN, DOUT as required on schematic. I also have some 3 and 9 chips from regular manufacturer but they don't work reliable on such MBs either.

The KMC MB is one that boots without parity but I have to go to setup 1st boot and disable parity otherwise it will locks on parity error next boot (with non-parity SIMMs). With parity SIMMs it works as expected so if there would be a problem with parity I will get an error.

The Abit MB even couldn't POST with non-parity SIMMs (and they have to be fitted in bank 0 not bank 1), setup has options for parity disable (twice 🤣, at advanced settings and one more in chipset settings page) but I didn't try to swap SIMMs after changing the setting to parity disabled if it really applies. But it is problematic as CMOS battery will discharge and will lost the settings it wouldn't boot anymore (with non-parity SIMMs).

I have some more 386DX MBs so I pull'em and try to make some small compatability list...

Possibly, your issue actually isn't the 4MB addressing scheme (this should already be "fixed" by using 9-chip modules, as 4M*1 chips typically only require refreshing of 1024 rows), but the total amount of memory. If the chipset is able to perform relocation of 256 or 384KB, installing 4*4MB will push the highest RAM address beyond 16MB, which requires A24 on the processor side. It is possible that there are not enough tag bits to make more than 16MB cacheable, e.g. a common configuration would be 64KB of cache and 8 tag bits, providing 16MB cacheable area. If the mainboards disregards A24 for the tag comparison, but does not consider everything above 16MB as non-cacheable, you will get the symptom that the systems fails spectaculary as soon as the last 256KB and the first 256KB of RAM are used at the same time, because they will be mixed up in the cache.

This is not just a hypothetical idea, I had exactly that problem on a 486 boards that I populated with 8*4MB. While 256KB cache and 8 tag bits would be sufficient to get a cacheable area of 64MB, ECS omitted the jumper that routes A25 to the tag comparator if you use 256KB cache, and thus only uses 7 bits of the tag RAM. The board works with 32MB installed if I either disable memory relocation, limiting the address space to just below 32MB, or add a non-cacheable area starting at 32MB in the setup.

If your issue of crashes with 4*4MB is due to cache aliasing (I know, it's a shot in the dark), these issues would disappear if you disable cache, which is quite quick to test if you have the system and RAM at hand.