jakethompson1 wrote on 2020-07-11, 18:49:I replied to an old thread so I'm the recent one here, but what you're saying sounds like my suspicion. Would that also be consi […]
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mkarcher wrote on 2020-07-11, 17:23:
My money is on "chipset autoconfiguration". Most BIOSes have the option to auto-configure RAM and cache timings automatically depending on the bus clock. On some BIOSes, auto-config is the only option (and no timing configuration is displayed in the advanced chipset setup). On most BIOSes, you can set auto-config to "disabled" and manually configure timings.
I replied to an old thread so I'm the recent one here, but what you're saying sounds like my suspicion. Would that also be consistent with Speedsys displaying 27 MHz?
The only performance-related options in the BIOS that I don't already understand are one about waiting 1T or none for FPU (I set it to none), and 1T or 2T for ELBA# (won't boot on 1T, default is 2T).
I think I have the jumpers set to max out all the VLB stuff now, and my issue is on some cold boots it locks up at the VGA BIOS copyright screen, and when it does boot, the memory graph in Speedsys beyond 256K is pretty unimpressive. Raw CPU performance, VESA Memory throughput, L1 and L2 cached memory, and disk I/O all look better though.
I know how to write asm to do i/o port reads and writes and such if I were curious about settings that don't show in the BIOS, but there seems to be very little documentation at that depth about the UMC 82C491F.
Yeah, good luck on finding UMC chipset data sheets. If your BIOS is AMI, you might want to try AMISETUP to get access to hidden configuration options. If your BIOS is AWARD; you might want to try MODBIN to create a modified BIOS for your board that exposes more configuration options. MODBIN is a tool aimed at mainboard manufacturers which lets them choose which of the options the chipset manufacturer provided should actually be exposed to the user. A deep understanding of mainboard operation is helpful for using MODBIN, Assembly language knownledge is not required, as MODBIN only edits configuration data in the BIOS, but it does nothing about code.
I guess the ELBA# pin means "external local bus access". This signal is driven by a VL card to indicate that the cycle is handled by a VL card and should thus not be handled by the ISA bridge or the memory controller, although I am unsure whether having VL memory space on top of mainboard memory is actually a supported configurtion on most 486 chipsets. The VL slots have a pin called "LDEV#" (local bus device) that is to be driven by a VL card if it wants to respond to a cycle. The LDEV# signals of all VL slots (and onboard local-bus devices, if any) are typically ANDed together using a fast AND gate chip (remember, LDEV# is active low, so a physical "AND" gate actually means "OR"), and presented to the chipset. It seems UMC calls this OR of any LDEV# line "ELBA#".
The setup option is about when the chipset is going to theck its ELBA# input pin. It must not start an ISA cycle for cycles handled by VL cards, so it cannot forward the 486 cycle to the ISA bus until the decision for VL/non-VL is known, so it needs to wait for the ELBA# check result before forwarding. The fast option is T1, and it means that at the end of the first clock cycle of an 486 bus cycle, LDEV is sampled. The chipset looses one clock before it may assert any read/write command lines on the ISA bus. This might not be an issue because there might be address setup time requirements on the ISA bus that require a command delay anyway. The slower option is T2, which gives VL cards a whole extra cycle to assert LDEV#, but also delays forwarding of cycles to the ISA bus by an extra FSB cycle.
Disregarding the delay of the AND gate that computes ELBA# from LDEV#, the recommendation of VESA is to sample LDEV# at the end of T1 if clock speed is 33MHz or lower, and to sample LDEV# at the end of T2 if clock speed is above 33MHz. This is what the VL>33MHz jumper on the mainboard is for. It does not have any effect on mainboard operation itself, its only function is to drive the ID3 pin on VL bus that informs cards about the bus speed. Setting this jumper to >33Mhz, it tells the VL cards that it is OK to take an extra cycle on decoding the address, because LDEV is sampled at the end of T2. Setting this jumper to >33MHz and configuring ELBA# sampling to T1 is a non-conforming configuration. The second VL jumper is about write wait states. It also does not influence mainboard operation at all (on the mainboards I know), but it is directly connected to the ID2 pin. This pin tells VL cards that they can assume there are no 0WS write cycles on the VL bus, so taking an extra cycle to pick up the data on write cycles is OK, even if the card signals LRDY# (to indicate readiness, i.e. terminate the cycle) very early. Again, the VESA recommendation is that 0WS write cycles are forbidden at clock frequencies above 33MHz.
ELBA# at T2 is a performance killer for ISA performance, and if you need that configuration at 40MHz (or even at 33MHz), you should consider using a different mainboard, or you should place everything performance sensitive on the VL bus (mostly hard disk controller and graphics card) to avoid paying the ISA performance penalty during normal operation.
