pshipkov wrote on 2020-08-10, 02:07:
Yesterday i ran into exactly this issue.
same class ISSI chips, 10ns, two different series (id number) - incompatible with each other 😖
Experienced people on retro forums seem to agree that ISSI never manufactured 10ns DIP cache chips. Most likely all of the 10ns ISSI chips are counterfeit. Their quality is said to be wonky, as in "expect a dead-on-arrival rate of one-out-of ten chips". This does not mean for sure that (some of) the good ones are unable to meet the 10ns specifications, but you need to be prepared that these chips might be out-of-spec in one or the other way. Combining chips that are out-of-spec in different ways can easily result in problems.
Usually, you get the spec sheet telling you "we can't tell you excatly how long it takes after you disable chip-enable until the bus is really released, and how long it takes after you enable the chip until the bus is driven by the chip. The exact time for both claiming and releasing the bus depends on operating voltage at temperature. Yet we do tell you that releasing the bus is faster than claiming the bus, as long as all involved chips run at the same voltage and temperature". This means that if you run a bank-interleaved cache (as nearly all 8-chip 486 cache solutions to), you will not get bus conflicts if the chip enable signals of the two banks do not overlap (the chipset takes care of that), and all cache chips are of the same type. If you mix chips of different types, the guarantee about "releasing faster than claiming" is void. Considering that the ISSI 10ns chips are most likely re-marked chips from different sources, mixing different "series" of them might actually be mixing different chip types.
