3 or 9 pins shouldn't matter, other than for possible overclocking as 9 pin SIMMs put higher load on the bus which will tax the system harder. Both types will have parity and only other difference is that 3 chip ones have 8 data bits coming out of two chips rather than 8 where each handles only single bit. Parity is handred by dedicated single bit chip on both.

It can matter. The 3-chip modules have different refresh requirements. Older boards (80s-1991) will often actually require 9-chip modules. Otherwise the board doesn't properly refresh the memory.

maxtherabbit wrote on 2020-09-13, 21:58:

It can matter. The 3-chip modules have different refresh requirements. Older boards (80s-1991) will often actually require 9-chip modules. Otherwise the board doesn't properly refresh the memory.

To add background to this correct answer, let's look at a typical 256KB SIMM. It may consist of 9 chips of 256 kiloaddresses (kibiaddresses?) of one bit each. A typical model number of such a chip is 41256 (4 = DRAM, 1 = 1 bit per address, 256 = 256 kiloaddresses), e.g. the HYB41256 by Siemens. The datasheet says about refreshing:

HYB41256 wrote:

A refresh operation must be performed at least every four milliseconds to retain data. [...] Strobing each of the 256 row addresses (A0 through A7) with /RAS, causes all bits in each row to be refreshed.

So although the chip has address bits A0 to A8, you just need to count A0..A7 from 0 to 255 to refresh all bits of the chip. The eigth bit does not matter for refreshing at all. The four milliseconds is the time in which all rows need to be refreshed, so if you single rows one at a time (as the IBM PC/XT does), you need to refresh a row at least every 15.6 microseconds.

On the other hand, a three-chip module of 256KB contains all data bits in just two 44256-kind chips, e.g. the Samsung KM44C256B. Let's check the refresh requirement in the datasheet again. The bold-face highlighting has been added by me to make the differences more obvious.

KM44C256B wrote:

To maintain data integrity, it is necessary to refresh each of the rows every 8 ms. [...] the most common method for performing refresh [ is ] performed by strobing a row address with /RAS [...]. This cycle must be repeated each of the 512 row addresses (A0 - A8).

For this chip (and most other 256K x 4 chips), you need to count from 0 to 511 using A0 to A8. If you use 256K x 4 chips, an 8-bit counter will no longer do for refreshing. The rate of single row refreshes is still the same, though, at 8ms / 512 = 15.6 microseconds again.

The IBM PC is a nice example for why this difference matters: The ISA bus provides refresh signalling that can be used for memory expansion cards. It asserts the REFRESH line on the ISA bus while asserting an 8-bit count value on A0-A7. If a memory expansion card uses 256K x 4 chips, it needs to provide a valid A8 on its own (and most memory cards did).

Later memory chips (like the KM44C256B, but not the older HYB41256) have an internal counter, and can be told to "refresh the next row" without needing the row number on the address bits. This scheme is called "CAS-before-RAS" refresh and needs special support by the mainboard. If a mainboard uses CAS-before-RAS refresh, the number of rows in the RAM chip no longer matters for refreshing. All typical RAM chips (that support CAS-before-RAS) do just fine with one CAS-before-RAS refresh every 15.6microseconds, no matter how many rows they have internally.

Got it; thank you for the fantastic writeup!

maxtherabbit wrote on 2020-09-13, 21:58:

It can matter. The 3-chip modules have different refresh requirements. Older boards (80s-1991) will often actually require 9-chip modules. Otherwise the board doesn't properly refresh the memory.

Agree ! Without getting technical there are many old boards that do not like the 3 chip but work fine with 9 chip SIMMS.

mkarcher wrote on 2020-09-13, 22:37:

To add background to this correct answer, let's look at a typical 256KB SIMM...

Nice write up !

mkarcher wrote on 2020-09-13, 22:37:

HYB41256 wrote:

A refresh operation must be performed at least every four milliseconds to retain data. [...] Strobing each of the 256 row addresses (A0 through A7) with /RAS, causes all bits in each row to be refreshed.

So although the chip has address bits A0 to A8, you just need to count A0..A7 from 0 to 255 to refresh all bits of the chip. The eigth bit does not matter for refreshing at all. The four milliseconds is the time in which all rows need to be refreshed, so if you single rows one at a time (as the IBM PC/XT does), you need to refresh a row at least every 15.6 microseconds.

I was just thinking about this. Did the DRAM industry make special effort to design the 256Kx1 chips so that users would not have to redesign their refresh circuit when retrofitting their designs from 64Kx1 to 256Kx1 DRAM, or is there something inherent to the 256Kx1 design internally that makes the refresh work that way?

I'm pretty sure 1bit exists to make big system memories possible, without doing any address decode to select between different chips since any extra logic means a slower system. The same amount of silicon still fits roughly as many individual bits regarless of chip databus witdh, so you can make a 1bit chip that uses entire array for itself and on the host board you can use as many of each as wide as the system bus is, and all of this comes from one RAS+CAS pair. It was one way to wait for Moore's law to catch up with bigger/denser and faster chips 🤣.
256k rows specifically does sound like it mattered to try to keep the 8bit counter scheme described earlier still workable.

jakethompson1 wrote on 2024-08-06, 00:43:

I was just thinking about this. Did the DRAM industry make special effort to design the 256Kx1 chips so that users would not have to redesign their refresh circuit when retrofitting their designs from 64Kx1 to 256Kx1 DRAM, or is there something inherent to the 256Kx1 design internally that makes the refresh work that way?

I suppose all 256kbit RAMs are internally built the same way, both 64K x 4 and 256K x 1 chips. Typically, the row/column drivers are located in a plus-formed shape with four quadratic bit arrays in the corners of the chip. In a 64K x 4 chip, the four bits that are accessed simultaneously are taken one from each bit array. Each of the bit arrays has 256 columns and 256 rows. Opening a row means opening one of the 256 rows of 256 columns each in each of the four bit arrays. In a 256K x 1 chip, the storage matrix works identically, and the top address bit (both the top row address bit and the top column address bit) is used to select one of the four fields. As opening a row opens a row in all fields, after opening 256 different rows, all rows have been opened.

Furthermore, kind of arrangement is also the reason for the short-lived "nibble mode" memory. This was an alternative memory before FPM turned out to be the standard RAM type. "nibble mode" memory is a special kind of x1 chip, in which you can cycle through the four fields by pulsing /CAS during a cycle, which is essentially a four-bit burst. While you can access different columns in FPM keeping the same page open, in nibble mode memory, you can not select another column without starting a new /RAS-/CAS cycle.