This is almost certainly setting for L1 cache.
Don't have experience with this particular adaptor. But I am not sure disabling cache is what the "pass through" means. That wouldn't make any sense and not sure if a passive adaptor even could do that. I would read it as "do not do anything" or "respect motherboard setting".
Many motherboards do have settings for L1 cache mode or multiplier. If you do the same on the interposer this can lead to undefined behaviour as you are effectively setting high/low/floating the CPU pin twice in serial. On the other hand no interposer can reliably enable WB unless the motherboard has support for it, so "WB" setting on the interposer wouldn't make any sense.
If I were designing an adaptor like this I'd certainly want to have option to either force write-through (by floating WB/WT pinout) or passthrough (do nothing). And the same for the multiplier.
derSammler wrote on 2019-09-02, 08:25:
The L1 cache is inside the CPU. The rest of the system won't care or even notice whether it's WT or WB.
This is simply not true. In order to be able to run L1 in WB you need to have solid provisions for cache coherency in place. So the rest of your system (chipset and possibly other bus masters let alone other CPUs) has to be well aware of the fact you are running WB. There has to be mechanism for invalidating cache during WB cycle. That's what these extra WB pins are there for and there was such a big deal about L1 WB support and only newer 486 boards can support it (if lucky). Otherwise the system would crash really fast.