AV9107-03 generates frequencies from 2 to 120 MHz
AV9107-04 12.5 - 130 MHz
AV9107-05 40 - 80 MHz
AV9107-10 25 - 50 MHz
though these last two are DIP 8 packages

too bad for the lack of datasheet for the part that is on your mainboard. KDN-0147C
you can look at the AV9107 info, trace the FS0-FS3 pins and give it to old trial and error approach. 😀
Just make sure you don't short any voltage rails directly to ground.

5x86 support does not require any oscillator changes, that CPU runs at 33 MHz bus speed like most 486s.

What you need is a jumper that sets DX4 internal multiplier to x2 instead of the default x3, as the 5x86 maps x2 to x4 internally to run at 133MHz. Other than that the settings should be the same that an Enhanced AMD DX4.

TheMobRules wrote on 2021-04-23, 13:43:

5x86 support does not require any oscillator changes, that CPU runs at 33 MHz bus speed like most 486s.

What you need is a jumper that sets DX4 internal multiplier to x2 instead of the default x3, as the 5x86 maps x2 to x4 internally to run at 133MHz. Other than that the settings should be the same that an Enhanced AMD DX4.

Indeed. Too bad they don't specify multiplier settings in the manual. 🙁

It may be undocumented, if the board was released before the 5x86 (had this happen to me with a PCChips M921). If you feel like doing some detective work, you can use a multimeter to find a pin in the jumper header area that is connected to the CLKMUL pin of the CPU socket. If you find one, there is probably another pin next to it that connects to GND. Short those two with a jumper cap, and you get DX4 2x (or 5x86 4x).

That post string confirms that it's an iston motherboard.

TheMobRules wrote on 2021-04-23, 15:32:

It may be undocumented, if the board was released before the 5x86 (had this happen to me with a PCChips M921). If you feel like doing some detective work, you can use a multimeter to find a pin in the jumper header area that is connected to the CLKMUL pin of the CPU socket. If you find one, there is probably another pin next to it that connects to GND. Short those two with a jumper cap, and you get DX4 2x (or 5x86 4x).

I'm waiting for new test leads for my multimeter. Once they arrive, then I can start thinking of doing some detective work. I might also have a look at the jumper settings of different CPU models to see which are the same and which are different between AMD, Cyrix and Intel models, and try to figure out which jumpers specify model of CPU and which might indicate multiplier. However, I've read that on some boards, it doesn't work that logically, but that it's the combination of several jumpers that set multiplier for example. I don't get why they couldn't all just have a small bank of jumpers for "manufacturer", "multiplier", "WT/WB" and "Bus Clock". I guess that was too logical for the early 90's.

LunarG wrote on 2021-04-23, 20:39:

[ and try to figure out which jumpers specify model of CPU and which might indicate multiplier.

You do not specify model by use of jumpers.
You just set some signal to be routed here or there or use this voltage and set this pin in this state (high or low or floating)
And the pin that indicate multiplier... pretty sure they're all known and identified on all the available pinouts floating around on the net.
Though their meaning sometimes depends on the model of cpu installed.
Some a bit easier to decipher than others.

weedeewee wrote on 2021-04-23, 21:32:

You do not specify model by use of jumpers. You just set some signal to be routed here or there or use this voltage and set thi […]
Show full quote

LunarG wrote on 2021-04-23, 20:39:

[ and try to figure out which jumpers specify model of CPU and which might indicate multiplier.

You do not specify model by use of jumpers.
You just set some signal to be routed here or there or use this voltage and set this pin in this state (high or low or floating)
And the pin that indicate multiplier... pretty sure they're all known and identified on all the available pinouts floating around on the net.
Though their meaning sometimes depends on the model of cpu installed.
Some a bit easier to decipher than others.

Well, since for example Intel 486DX uses different settings to AMD 486DX which uses different settings to Cyrix 486DX then you clearly set which model CPU it is. Not for the purpose of ID, but because there are differences between feature sets. And there's also differences in jumper settings between Intel models with and without added power management features...obviously. And different settings for standard AMD 486s and enhanced models (those with more cache and power management). You can call it what you will, I'd claim that you're specifying the model of CPU. And I'm not claiming that you tell the BIOS what kind of CPU it is. Obviously not. I'm talking about from an electrical point of view.

I think this is the slightly unhelpful manual:
https://www.elhvb.com/webhq/models/486vlb3/s486g.htm

Motherboard manual's not very helpful here. It just gives a bunch of 16 jumper settings (not including JP30, although that clearly should be in the middle of the listed ones) for each model CPU it supports. It's probably possible to work back to what each jumper actually does by comparing jumper settings with CPU pinouts. Sounds like that'd take some time.

LunarG wrote on 2021-04-23, 21:54:

Well, since for example Intel 486DX uses different settings to AMD 486DX which uses different settings to Cyrix 486DX

I get what you're going for but I have to say that is a partially bad example 😀
I can't say I've ever seen any mainboard have different jumpersettings for the intel 486DX and AMD 846DX
The Cyrix, absolutely has different jumpers, but not the other two. They tend to get listed separately in the manual, yet the jumpers are identical, like some others.
the board manual i'm looking at even has the same for intel and amd 486DX2, and only one jumper different for DX4 .
Anyway. I wish you well and good hunting with your detective work and may your new testleads arrive quickly and be well suited for the task at hand.

I found a website with a table showing pin configs for different 486s. It shows lists "Intel DX4 (AMD 5x86)" in the same column, suggesting that I can just set my motherboard to P24C settings, and it should work perfectly with my 5x86. Also, since I'm getting 100MHz running the settings for "AMD DX-Plus", I'm guessing that running the "Clkmult" pin low, sets multiplier to 3X and setting it high, would change it to 4X. I'm going to have a look at this later, cause right now I'm in the middle of doing dishes (just got some things sitting to soak).

Right. I did a makeshift repair of my old test leads... I got impatient. I found that R17 on the CPU socket (where DX4 and Am5x86 are supposed to receive signal for CLKMUL) goes to JP30 pin 2 and JP32 pin 1.
The board boots with Intel DX4 settings using my Am5x86, no problem, but Chkcpu claims that L1 cache is enabled in Write-Through mode. It's set to Write-Back in BIOS.
I've found a few good sites today though, so I'm feeling more confident that I can get both WB L1 cache and 4x multiplier working soon.

LunarG wrote on 2021-04-24, 15:23:

The board boots with Intel DX4 settings using my Am5x86, no problem, but Chkcpu claims that L1 cache is enabled in Write-Through mode. It's set to Write-Back in BIOS.

The AMD and Intel DX4 / 5x86 processors do not support software-selectable L1 mode. The BIOS setting is only effective on Cyrix 486 / 5x86 CPUs. You need to find a jumper that sets the cache mode to get the DX4 / 5x86 into L1 WB. Of course , this only works if the board supports L1WB on (enhanced) Intel DX4 / Am5x86 / low-voltage Cyrix 486/5x86 processors at all. (it's the same bus protocol on those processors, but it is different on classic Cyrix processors and the PODP).

mkarcher wrote on 2021-04-24, 19:06:

LunarG wrote on 2021-04-24, 15:23:

The board boots with Intel DX4 settings using my Am5x86, no problem, but Chkcpu claims that L1 cache is enabled in Write-Through mode. It's set to Write-Back in BIOS.

The AMD and Intel DX4 / 5x86 processors do not support software-selectable L1 mode. The BIOS setting is only effective on Cyrix 486 / 5x86 CPUs. You need to find a jumper that sets the cache mode to get the DX4 / 5x86 into L1 WB. Of course , this only works if the board supports L1WB on (enhanced) Intel DX4 / Am5x86 / low-voltage Cyrix 486/5x86 processors at all. (it's the same bus protocol on those processors, but it is different on classic Cyrix processors and the PODP).

My motherboard does specify settings for the P24D (DX2-WB), although I suppose it can support the CPU without actually implementing support for WB L1 cache. That wouldn't make much sense though.

Partial success! 😁
Got the multiplier working. Running Intel DX4 settings at the moment. As soon as I got the multiplier set, it reported as the correct CPU in POST, rather than 486DX4-Plus.
So next goal is to get WB L1 cache. 😀

Nice! L1 WB may be a bit trickier, since it involves connecting several lines between the CPU and chipset, so that may require more than one jumper depending on how the motherboard was designed.

This page is a good resource if you want to figure out the correct jumper(s) for L1 WB in a 5x86 among other things.

TheMobRules wrote on 2021-04-24, 20:27:

Nice! L1 WB may be a bit trickier, since it involves connecting several lines between the CPU and chipset, so that may require more than one jumper depending on how the motherboard was designed.

This page is a good resource if you want to figure out the correct jumper(s) for L1 WB in a 5x86 among other things.

Yes, I found that page earlier today. It's been an interesting read so far. I'm going to look into the instructions for WB L1 cache, and see where it takes me. 😀

Right. So I think I've finally tracked down all the signals I need.
The INV* signal I need comes from the output portion of the I/O pin called W/R* (pin 104 on the 85C471) and is used together with EADS to invalidate a cache line.
The CACHE* signal comes from pin 118 (PCD - Page Cache Disable). This is according to the datasheet for the 471 chipset described thusly: "Page cache disable pin reflects the state of the page attribute bits of the 80486 CPU. When using P24D or P24T CPU, this pin is defined as CACHE*" This should of course hold true for P24C-WB and 5x86 as well.
The HITM* comes from 85C471 pin 90.
And finally, the WB/WT* select pin needs to receive Vcc to go high and set L1 cache operation to WB mode.
So yeah. I think I'm getting close to being able to run my 5x86 with the intended write-back cache 😁