Did you check the rise time for the 5V line? If under 500 ms, it probably doesn't matter much.

Good idea on the multi-boot write-up. I did something similar for Win9x, NT4, W2K, and XP all on one hard drive using only the NT boot loader. The Ultimate Multi-Boot Windows Benching Machine

IanB wrote on 2017-01-31, 03:40:

Well I got the TI486SXL2 working on my T5200 with DMA cache flushing and a20 gate support. Here's a photo of the mods: t5200mod. […]
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Well I got the TI486SXL2 working on my T5200 with DMA cache flushing and a20 gate support.
Here's a photo of the mods:
t5200mod.jpg
The blue wire is the A20 gate and the yellow ones plus the IC are the recommended flush circuit from the TI486SXL2 databook (wired for serial cache).
I also had to patch the BIOS to switch the cache off on a warm restart as it was messing up the BIOS initialisation code.
I'm still not 100% convinced about the A20gate but if I disable the input, HIMEM complains which seems to indicate it's doing something.

feipoa wrote:

I see you are upgrading a Toshiba laptop. Not many of that around here. Does the laptop have a heatsink or heatsink fan on the CPU? If not, is there space for one? This CPU gets really hot and should really have at least a heatsink on it, especially in a confined area like a laptop.

Well it isn't really a laptop, just a 20lb luggable with an orange gas plasma display (I've seen it described as a lap-crusher!). There is enough space to add a heatsink and it seems to be stable.

feipoa wrote:

If I recall correctly, you will have problems with the SXL2 or DRx2 in 2x mode if using a grey-top Cyrix 83D87. In such a configuration, I believe the computer crashed with sound access. I will check my notes later today to confirm exactly what problem occurred. It is best to use a black-top Cyrix 83D87-33 or Cyrix 87DLC. I have not checked to see which IIT or ULSI FPUs have the same problem with the SXL in 2x mode, but the Cyrix FPUs are faster so it seems only natural to use them.

Did you confirm what the issue with the grey-top FPUs was. Would any black-top do or do they have to be manufactured after a certain date?

The CPU certainly runs faster than the DRx2 but not spectacularly so. e.g. the Doom timedemo is only about 10-15% faster but that's probably because the slow screen access is a limiting factor. Simple benchmarks show little or no difference because their test loop is small enough to fit in the cache on both processors.
Any other benchmarks you would recommend?

Hello. I am trying to get a 486DLC up &running in a 386 motherboard. One question please: You connected one end of the blue wire to the A20 gate on the CPU. Now, where does the other end of the blue wire go? AFAIK, the 8042 is elsewhere on the Toshiba 5200 mainboard.

Oh. I found it here: Toshiba T5200 mods and upgrades

😀...

"The A20 mod is a wire from Pin 8 of IC 43 to pin F13 (A20M#) of the 486 CPU (blue wire)".

But what does IC43 do? Can someone please explain this to me?

Thank you and best regards 😀

I want to run a 486DLC on a Soyo SY-19G 386 motherboard with an ETEQ 82C4901 cache controller. Unfortunately I cannot find a data sheet or any other documentation for the 82C4901 chip.
I am trying to get the HLDA-Signal from the cache controller in order to feed it into the FLUSH-circuit for my 486DLC. Any ideas?

alexthekid wrote on 2021-05-19, 16:53:

I want to run a 486DLC on a Soyo SY-19G 386 motherboard with an ETEQ 82C4901 cache controller.

Why not try BARB first? No support for hidden refresh in BIOS?

Deunan wrote on 2021-05-19, 19:35:

alexthekid wrote on 2021-05-19, 16:53:

I want to run a 486DLC on a Soyo SY-19G 386 motherboard with an ETEQ 82C4901 cache controller.

Why not try BARB first? No support for hidden refresh in BIOS?

Hello Deunan and thank you for your reply.
I checked the bios. The only thing I can do is to enable or disable "concurrent refresh". No hidden refresh option.

Never heard of that option. I'd still try that (on and off) with BARB and benchmark. It will be obvious if the CPU is flushing cache constantly, the performance will drop like a rock, possibly even below 386DX levels.
Obviously the HW mod is better but software is easier and faster to configure and try out. BTW I will be making similar mod for non-PC system (no ISA bus) so I figured I will take the memory write signal from chips directly. The problem I have is there is some on-board memory, and SIMM slots for extra, and I'm not yet sure if it's all wired together or not. Once I figure that out I might need more gates to cover all the memory banks - but it should in theory be good enough.

Deunan wrote on 2021-05-20, 09:02:

Never heard of that option. I'd still try that (on and off) with BARB and benchmark. It will be obvious if the CPU is flushing cache constantly, the performance will drop like a rock, possibly even below 386DX levels.
Obviously the HW mod is better but software is easier and faster to configure and try out. BTW I will be making similar mod for non-PC system (no ISA bus) so I figured I will take the memory write signal from chips directly. The problem I have is there is some on-board memory, and SIMM slots for extra, and I'm not yet sure if it's all wired together or not. Once I figure that out I might need more gates to cover all the memory banks - but it should in theory be good enough.

According to the BIOS Guide:
"Concurrent Refresh: Both the processor and the refresh hardware have access to the memory at the same time. If you switch this off, the processor has to wait until the refresh hardware has finished (it's a lot slower). Enabled recommended"

So far I couldn't get the CPU working properly with L1 Cache enabled with the BARB method. I think I will open another thread, especially for the 486DLC on my Soyo SY-19G mainboard.
I am rather helpless regarding various BIOS settings. With the default BIOS settings my PC wont even boot - it is stuck in the memory test loop.

Settings to consider would be (pardon my nonexistent knowledge):

System Boot Up CPU Speed: Low / High: My PC wont boot with the 486DLC if set to high.
Fast Gate A20 Option: Enabled/ Disabled: No clue here. More crashes if enabled.
Turbo switch option: Enabled/Disabled: If disabled I cannot change the CPU speed back to high after boot.
Concurrent Refresh: Enabled/Disabled: No clue here either.
Non-Cachable Block-0 Base:
Non-Cachable Block-0 Size:
Non-Cachable Block-1 Base:
Non-Cachable Block-1 Size: Do I have to select the non-cachable segments here? Or is it sufficient to do this in the CX486.CFG?
Page Mode: Enabled/ Disabled: No clue here as well.

How would I set up the BIOS?
If I use the 3rd-Party-Tool Cyrix.exe, what would be the correct command line if I want to set up the system for the BARB method?
My board doesn't support hidden refresh. So, with the BARB method the L1-cache will be discarded with each DRAM-resfresh, is this correct?

It's weird that your mobo doesn't boot in high speed - could be mobo cache issues. But if the button works lets worry about that one later.
Don't use fast A20 gate if you have issues, I've seen mobos (even have one) that don't actually implement it even though there is an option to enable it. Not a big deal in most cases.

Leave the block settings alone, if the BIOS exposes them but only 2 out of 4, then it's possible it actually tries to configure the DLC - but maybe in a wrong way. Once you boot into DOS, assuming you can at all, run Cyrix.exe -q to show the settings. Paste them here, I can tell you if the BIOS is DLC-aware or not and what to try next.

And yes, if the refresh is done like on older XT/AT systems where there is fake DMA transaction to get CPU off the bus to refresh memory then using BARB will flush cache each time this happens. And flush is not free, it slows the CPU down, so if it happens that frequently you get even worse perfomance than with 386DX.

Thank you Deunan. This is really helpful. I will run cyrix -q and post the results tonight. As for the cache: I am using a total of 32Kx8=256K with a 32K tag ram chip and they all are 15ns chips . The cache chips worked fine in my 486 board.

These are my BIOS settings. I am using slow (almost the slowest, DRAM read can be set to 4WS) memory and cache timings for now.
I disabled the two non-cachable segments:

I skipped config.sys and autoexec.bat and I ran cyrix -q:
(This is what cyrix.exe reports after boot - no drivers loaded, no changes in the 486DLC-config made.)

So from this output, can you tell me whether my BIOS is DLC-aware?
What should I do next?

I played around a little with the cyrix.exe, but maybe I screwed up completely. 😉
In summary I tried to do the same configuration as posted in page 1 of this thread and I ran some benchmarks.
This configuration was used for the following benchmarks:

Here is SYSINFO8:

Here is VGABENCH. I am currently using a really slow OAK VGA-Card with 512kb video memory.
When replacing the 486DLC with a 386DX-40 my system scores 14.3 in this test:

I only had Speedsys v4.78 ready for this test, which reports a 13MHz CPU-clock (Was it v6.00 , which works better with the 486DLC?). The reported benchmark score is with 10.47 somewhere between the 386 DX-40 and the 486DX2-50 (sorry for the bad image quality)

PC-TOOLS System Information benchmark:

PC-Player benchmark in 320x200:

My system seems to work somehow. It is way more stable then when I tried the FLUSH-method. I am still getting unexpected crashes and freezes sometimes (e.g. in Norton Commander or in the command line the cursor is still blinking but the system doesn't accept keyboard inputs anymore and Ctrl-Alt-Del doesnt't work; text output of various command line tools stop after a few letters and the system halts; Funny thing: When playing around with the Bios/Cyrix-settings I even found a config where the CPU only seemed to execute stuff while keys on the keyboard were pressed 😉 ).
I will test memory and other components next.
From these benchmarks, would you say that my system is using hidden refresh?

Which tests can I run to see whether the CPU is correctly configured?

Weird things are happening now. Maybe you were right Deunan and I do have faulty cache memory. Memory test halted during BIOS-POST at 1472kb (It should have gone up to 4M).

The POST-screen said "001472 KB OK" and CMOS Memory size mismatch, Press F1....
After saving the BIOS-settings my system booted with only 1472 KB.... until the next power OFF/ON.
Then the full 4M were detected (and after boot available) again.

I will test the system piece by piece.

I have a few suspects.

1st suspect is the chipset. I replaced the 66 MHz QCO with an 80MHz model in order to get the 486DLC running at 40MHz. Maybe my chipset doesn't like that?
2nd suspect is the cache memory. I haven't seen any weird things (so far... but no extensive testing yet) with the L2-Cache disabled.
Also I will replace the 486DLC with a 386DX-33 or DX-40 and see how the system behaves.
I will test the DRAM as well.

Is there a program to test the L2-Cache? My idea was to run memtest86 with and without L2-Cache enabled.
Anything else I should test? 😀

There's an old DOS program called Gold Memory, it's a pretty good RAM tester. Try that one too to see if you have any memory issues (note, cache issues will cause random memory failures but if you get a pretty repeatable addresses reported it's most likely RAM sticks).

Your 3DBench, PC Player and Norton SI results are all right on the money - I think you're right though; the VGA card is holding you back. As a comparison, with a 1MB CL-GD5428 and a DLC-40 I get:

3DBench: 24.3
PC Player: 6.8fps
Norton SI: 65.5

Can you try the following options:

cyrix.exe -e -b -f- -m -r -i1

-e, enable cpu cache
-b, use BARB cache flush mechanism
-f-, disable FLUSH cache flush mechanism
-m, enable caching of 64KB of each megabyte
-r, disable caching of the ROM area in 640-1024kb
-i1, inhibit the first non-cacheable region (it's disabling any caching of 0-32MB in your example)

Those settings got me the best overall performance on my board. My BIOS enabled FLUSH by default, but I'm not convinced it was actually implemented fully - Landmark synthetic scores improved by going to BARB instead.

Hello megatron-uk, thank you, I will try your suggested cyrix setting next.
During the last days I was busy with some tests. It seems that my board has 2 nasty limitations:

1.) The chipset is stable at 33MHz. The chipset doesn't like 40MHz.
2.) Even though the manual suggests that the board can use 128KB or 256KB cache - in reality it cannot. It fails with any other cache configuration than 64KB (8x8KB + 8KB TAG) (and yes, I verified the cache jumper settings thrice 😉). Has anyone ever seen this phenomenon - a board that cannot live up to what its manual claims? 😉
I tested the cache chips that were used for the 128KB (4x32K + 8K TAG) or 256KB (8x32K + 32K TAG) cache configurations in other mainboards. There were no problems in other mainboards.

Good thing is: The DLC works fine, but only at 33MHz and only with 64KB L2-Cache.

I guess, I'll have to find another Mainboard in order to get a 40MHz System

Ah, that sucks about the 40MHz stability!

alexthekid wrote on 2021-05-23, 10:59:

I guess, I'll have to find another Mainboard in order to get a 40MHz System

Well, that sucks, but at least you know that now rather than chasing phantom problems later. I've run some tests to actually see how much BARB affect performance - because it will flush cache on all DMA requests, be it write or read (unlike properly working FLUSH input that should only do that on writes). Which means even on systems with hidden refresh a DMA transfer to SoundBlaster type card to play sound samples is going to trigger it.

I've run Doom2 with -timedemo demo3, with sound configured and ESS688 card being present. These are the results on Cyrix 486DLC at 40MHz:

BARB: 4471 / 20113 / 6348 / 5041
FLUSH: 4471 / 19339 / 6151 / 5042

FLUSH in this case is actually not enabled, just BARB disabled, but unless there is a DMA writing to memory (which on this system could only be the floppy drive and I wasn't using it) it's the same performance. I still haven't gotten around to do the HW mod myself, reason being I actually want to tap memory write signals on SIMM slots directly rather than MEMW on ISA bus, that's because I want to test that for another system where there is no ISA bus.

First number is demo ticks, second is elapsed ticks in full screen (with status bar on the bottom) and normal resolution, third is minimal screen and low resolution, fourth is same as third but with -nosound to validate the idea.
As can be seen there is some performance impact but it's not huge (less than 4%), and Doom2 is playing sounds pretty often. That being said FLUSH should provide smoother experience and would probably affect SXL chips more. In general though I'd say if you experience performance drops with BARB that you can feel while sound is played then the program/game probably needs a way faster 486 CPU anyway.

alexthekid wrote on 2021-05-23, 10:59:

Hello megatron-uk, thank you, I will try your suggested cyrix setting next. During the last days I was busy with some tests. It […]
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Hello megatron-uk, thank you, I will try your suggested cyrix setting next.
During the last days I was busy with some tests. It seems that my board has 2 nasty limitations:

1.) The chipset is stable at 33MHz. The chipset doesn't like 40MHz.
2.) Even though the manual suggests that the board can use 128KB or 256KB cache - in reality it cannot. It fails with any other cache configuration than 64KB (8x8KB + 8KB TAG) (and yes, I verified the cache jumper settings thrice 😉). Has anyone ever seen this phenomenon - a board that cannot live up to what its manual claims? 😉
I tested the cache chips that were used for the 128KB (4x32K + 8K TAG) or 256KB (8x32K + 32K TAG) cache configurations in other mainboards. There were no problems in other mainboards.

Good thing is: The DLC works fine, but only at 33MHz and only with 64KB L2-Cache.

I guess, I'll have to find another Mainboard in order to get a 40MHz System

I had to go through three different sets of good chips before I found 256KB of sram chips that worked reliably at 40mhz with my motherboard. But that was me. When you are working with 25+year old parts, you can find all sorts of quirky behavior.