m0rd wrote on 2021-08-10, 02:33:
and it seems it has 64kb cache??? did the standard ps/2 286 have any cache and does other upgrade boards have cache??
I don't know about other upgrade boards, but the original PS/2 Model 30/286 (which is an entry-level PS/2 placed even below the Model 50) definitely didn't have memory cache. Possibly it didn't even need memory cache because memory was fast enough. In case of the upgrade module, consider that the 386SX on that module is clocked considerably faster than the original 286, so it also wants to access memory faster. The x86 architecture is quite dependent on memory performance, so slowing down the memory access of the upgrade module to the original PS/2 Model 30/286 memory speed would significantly reduce memory performance. Cache is needed to make an upgrade like this work.
Instead of having cache on the board, one could also just go 486, using one of those 16-bit bus 486 processors (Cyrix 486SLC (or it's second source SGS Thompson 486SLC) or IBM 486SLC (which is an entirely different chip)), which have integrated cache.
m0rd wrote on 2021-08-10, 02:33:
Can anyone tell by looking at the chips on it how much cache it should have???
The cache on your module consists of the fast CMOS SRAM chips on the board: 3 chips MB8298-25, and one chip labelled ATT7C174P. The MB8298-25 chips make up for 32 kilo addresses with 8 bits each. Two of these chips are used to form 32 kilo addresses of 16 bits (to match the 386SX bus width). 32K addresses that contain 16 bits is the same amount of data as 64K addresses that contain 8 bits (a byte), so that is 64K of cache RAM. The ATT7C174P chip is a very interesting chip: It is used as tag RAM (taking note what address is actually in cache), and does not only contain the cache, but it also integrates the comparator that tells the board whether the address the processor is trying to access right now is in the cache or not. This chip is for up to 8K cache lines, so the line size is 8 bytes or bigger. On a 386SX board, a line size of 4 words of 2 bytes each sounds likely. The last chip, the third MB8297-25 is most likely contains valid (and dirty?) bits telling which words of a cache line contain data, and which words are unknown.
I'm very sure there is no way to upgrade cache on that board. At those time, cache controllers were not designed to be flexible, but just to work for the one use case they are designed for. So this upgrade has 64K cache, and there is very likely no way to change that using (just) replacement ICs.